X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=88487bb77f6ef0772403330fe1f27a0c12138bad;hp=bb486c8fddc301fc1e50f5c21458469595ac0eb3;hb=12549f1161748215072541ed9a9c8625da041131;hpb=191ec8c5b7b6bb6b348a2c43b851923181fd68d8 diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index bb486c8..88487bb 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -2,7 +2,7 @@ ## This file is part of the libsigrokdecode project. ## ## Copyright (C) 2011 Gareth McMullin -## Copyright (C) 2012-2013 Uwe Hermann +## Copyright (C) 2012-2014 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -19,10 +19,31 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# SPI protocol decoder - import sigrokdecode as srd +''' +Protocol output format: + +SPI packet: +[, , ] + +Commands: + - 'DATA': contains the MISO data, contains the MOSI data. + The data is _usually_ 8 bits (but can also be fewer or more bits). + Both data items are Python numbers (not strings), or None if the respective + probe was not supplied. + - 'CS CHANGE': is the old CS# pin value, is the new value. + Both data items are Python numbers (0/1), not strings. + +Examples: + ['CS-CHANGE', 1, 0] + ['DATA', 0xff, 0x3a] + ['DATA', 0x65, 0x00] + ['DATA', 0xa8, None] + ['DATA', None, 0x55] + ['CS-CHANGE', 0, 1] +''' + # Key: (CPOL, CPHA). Value: SPI mode. # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. @@ -43,14 +64,15 @@ class Decoder(srd.Decoder): inputs = ['logic'] outputs = ['spi'] probes = [ + {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, + ] + optional_probes = [ {'id': 'miso', 'name': 'MISO', - 'desc': 'SPI MISO line (Master in, slave out)'}, + 'desc': 'SPI MISO line (master in, slave out)'}, {'id': 'mosi', 'name': 'MOSI', - 'desc': 'SPI MOSI line (Master out, slave in)'}, - {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, - {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, + 'desc': 'SPI MOSI line (master out, slave in)'}, + {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, ] - optional_probes = [] # TODO options = { 'cs_polarity': ['CS# polarity', 'active-low'], 'cpol': ['Clock polarity', 0], @@ -60,31 +82,36 @@ class Decoder(srd.Decoder): 'format': ['Data format', 'hex'], } annotations = [ - ['MISO/MOSI data', 'MISO/MOSI SPI data'], - ['MISO data', 'MISO SPI data'], - ['MOSI data', 'MOSI SPI data'], - ['Warnings', 'Human-readable warnings'], + ['miso-data', 'MISO SPI data'], + ['mosi-data', 'MOSI SPI data'], + ['warnings', 'Human-readable warnings'], ] def __init__(self): + self.samplerate = None self.oldsck = 1 self.bitcount = 0 self.mosidata = 0 self.misodata = 0 - self.bytesreceived = 0 self.startsample = -1 self.samplenum = -1 self.cs_was_deasserted_during_data_word = 0 self.oldcs = -1 self.oldpins = None + self.have_cs = None + self.have_miso = None + self.have_mosi = None self.state = 'IDLE' - def start(self, metadata): - self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') - self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value - def report(self): - return 'SPI: %d bytes received' % self.bytesreceived + def start(self): + self.out_proto = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) + self.out_bitrate = self.register(srd.OUTPUT_META, + meta=(int, 'Bitrate', 'Bitrate during transfers')) def putpw(self, data): self.put(self.startsample, self.samplenum, self.out_proto, data) @@ -96,24 +123,27 @@ class Decoder(srd.Decoder): # If this is the first bit, save its sample number. if self.bitcount == 0: self.startsample = self.samplenum - active_low = (self.options['cs_polarity'] == 'active-low') - deasserted = cs if active_low else not cs - if deasserted: - self.cs_was_deasserted_during_data_word = 1 + if self.have_cs: + active_low = (self.options['cs_polarity'] == 'active-low') + deasserted = cs if active_low else not cs + if deasserted: + self.cs_was_deasserted_during_data_word = 1 ws = self.options['wordsize'] # Receive MOSI bit into our shift register. - if self.options['bitorder'] == 'msb-first': - self.mosidata |= mosi << (ws - 1 - self.bitcount) - else: - self.mosidata |= mosi << self.bitcount + if self.have_mosi: + if self.options['bitorder'] == 'msb-first': + self.mosidata |= mosi << (ws - 1 - self.bitcount) + else: + self.mosidata |= mosi << self.bitcount # Receive MISO bit into our shift register. - if self.options['bitorder'] == 'msb-first': - self.misodata |= miso << (ws - 1 - self.bitcount) - else: - self.misodata |= miso << self.bitcount + if self.have_miso: + if self.options['bitorder'] == 'msb-first': + self.misodata |= miso << (ws - 1 - self.bitcount) + else: + self.misodata |= miso << self.bitcount self.bitcount += 1 @@ -121,28 +151,41 @@ class Decoder(srd.Decoder): if self.bitcount != ws: return - self.putpw(['DATA', self.mosidata, self.misodata]) - self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) - self.putw([1, ['%02X' % self.misodata]]) - self.putw([2, ['%02X' % self.mosidata]]) + si = self.mosidata if self.have_mosi else None + so = self.misodata if self.have_miso else None - if self.cs_was_deasserted_during_data_word: - self.putw([3, ['CS# was deasserted during this data word!']]) + # Pass MOSI and MISO to the next PD up the stack. + self.putpw(['DATA', si, so]) + + # Annotations. + if self.have_miso: + self.putw([0, ['%02X' % self.misodata]]) + if self.have_mosi: + self.putw([1, ['%02X' % self.mosidata]]) + + # Meta bitrate. + elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1) + bitrate = int(1 / elapsed * self.options['wordsize']) + self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) + + if self.have_cs and self.cs_was_deasserted_during_data_word: + self.putw([2, ['CS# was deasserted during this data word!']]) # Reset decoder state. - self.mosidata = 0 - self.misodata = 0 + self.misodata = 0 if self.have_miso else None + self.mosidata = 0 if self.have_mosi else None self.bitcount = 0 - # Keep stats for summary. - self.bytesreceived += 1 - def find_clk_edge(self, miso, mosi, sck, cs): - if self.oldcs != cs: + if self.have_cs and self.oldcs != cs: # Send all CS# pin value changes. self.put(self.samplenum, self.samplenum, self.out_proto, ['CS-CHANGE', self.oldcs, cs]) self.oldcs = cs + # Reset decoder state when CS# changes (and the CS# pin is used). + self.misodata = 0 if self.have_miso else None + self.mosidata = 0 if self.have_mosi else None + self.bitcount = 0 # Ignore sample if the clock pin hasn't changed. if sck == self.oldsck: @@ -165,13 +208,18 @@ class Decoder(srd.Decoder): self.handle_bit(miso, mosi, sck, cs) def decode(self, ss, es, data): - # TODO: Either MISO or MOSI could be optional. CS# is optional. + if self.samplerate is None: + raise Exception("Cannot decode without samplerate.") + # Either MISO or MOSI can be omitted (but not both). CS# is optional. for (self.samplenum, pins) in data: # Ignore identical samples early on (for performance reasons). if self.oldpins == pins: continue - self.oldpins, (miso, mosi, sck, cs) = pins, pins + self.oldpins, (sck, miso, mosi, cs) = pins, pins + self.have_miso = (miso in (0, 1)) + self.have_mosi = (mosi in (0, 1)) + self.have_cs = (cs in (0, 1)) # State machine. if self.state == 'IDLE':