X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=85bb1cb9e3195464fc55a983d3e87ecc78cf0baf;hp=5c7df196370f2643378697199a63a3490dae1375;hb=f04db50ab7bbc59b7668396500b92ae2d3418f0e;hpb=34929ee00c976842196ca95240b6cb1a7f5d8c75 diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 5c7df19..85bb1cb 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -15,11 +15,13 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd +from collections import namedtuple + +Data = namedtuple('Data', ['ss', 'es', 'val']) ''' OUTPUT_PYTHON format: @@ -34,10 +36,16 @@ Packet: channel was not supplied. - 'BITS': / contain a list of bit values in this MOSI/MISO data item, and for each of those also their respective start-/endsample numbers. - - 'CS CHANGE': is the old CS# pin value, is the new value. - Both data items are Python numbers (0/1), not strings. + - 'CS-CHANGE': is the old CS# pin value, is the new value. + Both data items are Python numbers (0/1), not strings. At the beginning of + the decoding a packet is generated with = None and being the + initial state of the CS# pin or None if the chip select pin is not supplied. + - 'TRANSFER': / contain a list of Data() namedtuples for each + byte transferred during this block of CS# asserted time. Each Data() has + fields ss, es, and val. Examples: + ['CS-CHANGE', None, 1] ['CS-CHANGE', 1, 0] ['DATA', 0xff, 0x3a] ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], @@ -48,6 +56,8 @@ Examples: ['DATA', 0xa8, None] ['DATA', None, 0x55] ['CS-CHANGE', 0, 1] + ['TRANSFER', [Data(ss=80, es=96, val=0xff), ...], + [Data(ss=80, es=96, val=0x3a), ...]] ''' # Key: (CPOL, CPHA). Value: SPI mode. @@ -60,14 +70,11 @@ spi_mode = { (1, 1): 3, # Mode 3 } -class SamplerateError(Exception): - pass - -class MissingDataError(Exception): +class ChannelError(Exception): pass class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'spi' name = 'SPI' longname = 'Serial Peripheral Interface' @@ -108,33 +115,42 @@ class Decoder(srd.Decoder): ('mosi-bits', 'MOSI bits', (3,)), ('other', 'Other', (4,)), ) + binary = ( + ('miso', 'MISO'), + ('mosi', 'MOSI'), + ) def __init__(self): + self.reset() + + def reset(self): self.samplerate = None - self.oldclk = 1 self.bitcount = 0 self.misodata = self.mosidata = 0 self.misobits = [] self.mosibits = [] - self.startsample = -1 + self.misobytes = [] + self.mosibytes = [] + self.ss_block = -1 self.samplenum = -1 + self.ss_transfer = -1 self.cs_was_deasserted = False - self.oldcs = -1 - self.oldpins = None self.have_cs = self.have_miso = self.have_mosi = None - def metadata(self, key, value): - if key == srd.SRD_CONF_SAMPLERATE: - self.samplerate = value - def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) self.out_ann = self.register(srd.OUTPUT_ANN) + self.out_binary = self.register(srd.OUTPUT_BINARY) self.out_bitrate = self.register(srd.OUTPUT_META, meta=(int, 'Bitrate', 'Bitrate during transfers')) + self.bw = (self.options['wordsize'] + 7) // 8 + + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value def putw(self, data): - self.put(self.startsample, self.samplenum, self.out_ann, data) + self.put(self.ss_block, self.samplenum, self.out_ann, data) def putdata(self): # Pass MISO and MOSI bits and then data to the next PD up the stack. @@ -145,12 +161,21 @@ class Decoder(srd.Decoder): if self.have_miso: ss, es = self.misobits[-1][1], self.misobits[0][2] + bdata = so.to_bytes(self.bw, byteorder='big') + self.put(ss, es, self.out_binary, [0, bdata]) if self.have_mosi: ss, es = self.mosibits[-1][1], self.mosibits[0][2] + bdata = si.to_bytes(self.bw, byteorder='big') + self.put(ss, es, self.out_binary, [1, bdata]) self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits]) self.put(ss, es, self.out_python, ['DATA', si, so]) + if self.have_miso: + self.misobytes.append(Data(ss=ss, es=es, val=so)) + if self.have_mosi: + self.mosibytes.append(Data(ss=ss, es=es, val=si)) + # Bit annotations. if self.have_miso: for bit in self.misobits: @@ -172,27 +197,30 @@ class Decoder(srd.Decoder): self.mosibits = [] if self.have_mosi else None self.bitcount = 0 + def cs_asserted(self, cs): + active_low = (self.options['cs_polarity'] == 'active-low') + return (cs == 0) if active_low else (cs == 1) + def handle_bit(self, miso, mosi, clk, cs): # If this is the first bit of a dataword, save its sample number. if self.bitcount == 0: - self.startsample = self.samplenum - self.cs_was_deasserted = False - if self.have_cs: - active_low = (self.options['cs_polarity'] == 'active-low') - self.cs_was_deasserted = (cs == 1) if active_low else (cs == 0) + self.ss_block = self.samplenum + self.cs_was_deasserted = \ + not self.cs_asserted(cs) if self.have_cs else False ws = self.options['wordsize'] + bo = self.options['bitorder'] # Receive MISO bit into our shift register. if self.have_miso: - if self.options['bitorder'] == 'msb-first': + if bo == 'msb-first': self.misodata |= miso << (ws - 1 - self.bitcount) else: self.misodata |= miso << self.bitcount # Receive MOSI bit into our shift register. if self.have_mosi: - if self.options['bitorder'] == 'msb-first': + if bo == 'msb-first': self.mosidata |= mosi << (ws - 1 - self.bitcount) else: self.mosidata |= mosi << self.bitcount @@ -224,30 +252,42 @@ class Decoder(srd.Decoder): self.putdata() # Meta bitrate. - elapsed = 1 / float(self.samplerate) - elapsed *= (self.samplenum - self.startsample + 1) - bitrate = int(1 / elapsed * self.options['wordsize']) - self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) + if self.samplerate: + elapsed = 1 / float(self.samplerate) + elapsed *= (self.samplenum - self.ss_block + 1) + bitrate = int(1 / elapsed * ws) + self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate) if self.have_cs and self.cs_was_deasserted: self.putw([4, ['CS# was deasserted during this data word!']]) self.reset_decoder_state() - def find_clk_edge(self, miso, mosi, clk, cs): - if self.have_cs and self.oldcs != cs: + def find_clk_edge(self, miso, mosi, clk, cs, first): + if self.have_cs and (first or self.matched[self.have_cs]): # Send all CS# pin value changes. + oldcs = None if first else 1 - cs self.put(self.samplenum, self.samplenum, self.out_python, - ['CS-CHANGE', self.oldcs, cs]) - self.oldcs = cs + ['CS-CHANGE', oldcs, cs]) + + if self.cs_asserted(cs): + self.ss_transfer = self.samplenum + self.misobytes = [] + self.mosibytes = [] + else: + self.put(self.ss_transfer, self.samplenum, self.out_python, + ['TRANSFER', self.mosibytes, self.misobytes]) + # Reset decoder state when CS# changes (and the CS# pin is used). self.reset_decoder_state() - # Ignore sample if the clock pin hasn't changed. - if clk == self.oldclk: + # We only care about samples if CS# is asserted. + if self.have_cs and not self.cs_asserted(cs): return - self.oldclk = clk + # Ignore sample if the clock pin hasn't changed. + if first or not self.matched[0]: + return # Sample data on rising/falling clock edge (depends on mode). mode = spi_mode[self.options['cpol'], self.options['cpha']] @@ -263,23 +303,35 @@ class Decoder(srd.Decoder): # Found the correct clock edge, now get the SPI bit(s). self.handle_bit(miso, mosi, clk, cs) - def decode(self, ss, es, data): - if not self.samplerate: - raise SamplerateError("Cannot decode without samplerate.") - # Either MISO or MOSI can be omitted (but not both). CS# is optional. - for (self.samplenum, pins) in data: - - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins, (clk, miso, mosi, cs) = pins, pins - self.have_miso = (miso in (0, 1)) - self.have_mosi = (mosi in (0, 1)) - self.have_cs = (cs in (0, 1)) - - # Either MISO or MOSI (but not both) can be omitted. - if not (self.have_miso or self.have_mosi): - raise MissingDataError('Either MISO or MOSI (or both) pins required.') - - self.find_clk_edge(miso, mosi, clk, cs) - + def decode(self): + # The CLK input is mandatory. Other signals are (individually) + # optional. Yet either MISO or MOSI (or both) must be provided. + # Tell stacked decoders when we don't have a CS# signal. + if not self.has_channel(0): + raise ChannelError('Either MISO or MOSI (or both) pins required.') + self.have_miso = self.has_channel(1) + self.have_mosi = self.has_channel(2) + if not self.have_miso and not self.have_mosi: + raise ChannelError('Either MISO or MOSI (or both) pins required.') + self.have_cs = self.has_channel(3) + if not self.have_cs: + self.put(0, 0, self.out_python, ['CS-CHANGE', None, None]) + + # We want all CLK changes. We want all CS changes if CS is used. + # Map 'have_cs' from boolean to an integer index. This simplifies + # evaluation in other locations. + wait_cond = [{0: 'e'}] + if self.have_cs: + self.have_cs = len(wait_cond) + wait_cond.append({3: 'e'}) + + # "Pixel compatibility" with the v2 implementation. Grab and + # process the very first sample before checking for edges. The + # previous implementation did this by seeding old values with + # None, which led to an immediate "change" in comparison. + (clk, miso, mosi, cs) = self.wait({}) + self.find_clk_edge(miso, mosi, clk, cs, True) + + while True: + (clk, miso, mosi, cs) = self.wait(wait_cond) + self.find_clk_edge(miso, mosi, clk, cs, False)