X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=7e4a1e5f9aaf5bedce191815b1d3cbb4e444d3de;hp=bb486c8fddc301fc1e50f5c21458469595ac0eb3;hb=0702e0cf5a0577122c4008007151b6c3d798b0fb;hpb=191ec8c5b7b6bb6b348a2c43b851923181fd68d8

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index bb486c8..7e4a1e5 100644
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -23,6 +23,26 @@
 
 import sigrokdecode as srd
 
+'''
+Protocol output format:
+
+SPI packet:
+[<cmd>, <data1>, <data2>]
+
+Commands:
+ - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
+   The data is _usually_ 8 bits (but can also be fewer or more bits).
+   Both data items are Python numbers, not strings.
+ - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
+   Both data items are Python numbers (0/1), not strings.
+
+Examples:
+ ['CS-CHANGE', 1, 0]
+ ['DATA', 0xff, 0x3a]
+ ['DATA', 0x65, 0x00]
+ ['CS-CHANGE', 0, 1]
+'''
+
 # Key: (CPOL, CPHA). Value: SPI mode.
 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
@@ -48,9 +68,10 @@ class Decoder(srd.Decoder):
         {'id': 'mosi', 'name': 'MOSI',
          'desc': 'SPI MOSI line (Master out, slave in)'},
         {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
-        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
     ]
-    optional_probes = [] # TODO
+    optional_probes = [
+        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
+    ]
     options = {
         'cs_polarity': ['CS# polarity', 'active-low'],
         'cpol': ['Clock polarity', 0],
@@ -96,10 +117,11 @@ class Decoder(srd.Decoder):
         # If this is the first bit, save its sample number.
         if self.bitcount == 0:
             self.startsample = self.samplenum
-            active_low = (self.options['cs_polarity'] == 'active-low')
-            deasserted = cs if active_low else not cs
-            if deasserted:
-                self.cs_was_deasserted_during_data_word = 1
+            if self.have_cs:
+                active_low = (self.options['cs_polarity'] == 'active-low')
+                deasserted = cs if active_low else not cs
+                if deasserted:
+                    self.cs_was_deasserted_during_data_word = 1
 
         ws = self.options['wordsize']
 
@@ -130,19 +152,19 @@ class Decoder(srd.Decoder):
             self.putw([3, ['CS# was deasserted during this data word!']])
 
         # Reset decoder state.
-        self.mosidata = 0
-        self.misodata = 0
-        self.bitcount = 0
+        self.mosidata = self.misodata = self.bitcount = 0
 
         # Keep stats for summary.
         self.bytesreceived += 1
 
     def find_clk_edge(self, miso, mosi, sck, cs):
-        if self.oldcs != cs:
+        if self.have_cs and self.oldcs != cs:
             # Send all CS# pin value changes.
             self.put(self.samplenum, self.samplenum, self.out_proto,
                      ['CS-CHANGE', self.oldcs, cs])
             self.oldcs = cs
+            # Reset decoder state when CS# changes (and the CS# pin is used).
+            self.mosidata = self.misodata = self.bitcount= 0
 
         # Ignore sample if the clock pin hasn't changed.
         if sck == self.oldsck:
@@ -172,6 +194,7 @@ class Decoder(srd.Decoder):
             if self.oldpins == pins:
                 continue
             self.oldpins, (miso, mosi, sck, cs) = pins, pins
+            self.have_cs = (cs in (0, 1))
 
             # State machine.
             if self.state == 'IDLE':