X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=7e4a1e5f9aaf5bedce191815b1d3cbb4e444d3de;hp=47bbe322a3342e8c5ee548c3e1c8c947f3725b39;hb=0702e0cf5a0577122c4008007151b6c3d798b0fb;hpb=29f8bb7b787ff8bc2a2e55d3de0b53452e73c6af diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 47bbe32..7e4a1e5 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -23,6 +23,26 @@ import sigrokdecode as srd +''' +Protocol output format: + +SPI packet: +[, , ] + +Commands: + - 'DATA': contains the MISO data, contains the MOSI data. + The data is _usually_ 8 bits (but can also be fewer or more bits). + Both data items are Python numbers, not strings. + - 'CS CHANGE': is the old CS# pin value, is the new value. + Both data items are Python numbers (0/1), not strings. + +Examples: + ['CS-CHANGE', 1, 0] + ['DATA', 0xff, 0x3a] + ['DATA', 0x65, 0x00] + ['CS-CHANGE', 0, 1] +''' + # Key: (CPOL, CPHA). Value: SPI mode. # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. @@ -48,9 +68,10 @@ class Decoder(srd.Decoder): {'id': 'mosi', 'name': 'MOSI', 'desc': 'SPI MOSI line (Master out, slave in)'}, {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, - {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, ] - optional_probes = [] # TODO + optional_probes = [ + {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, + ] options = { 'cs_polarity': ['CS# polarity', 'active-low'], 'cpol': ['Clock polarity', 0], @@ -77,6 +98,7 @@ class Decoder(srd.Decoder): self.cs_was_deasserted_during_data_word = 0 self.oldcs = -1 self.oldpins = None + self.state = 'IDLE' def start(self, metadata): self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') @@ -91,6 +113,79 @@ class Decoder(srd.Decoder): def putw(self, data): self.put(self.startsample, self.samplenum, self.out_ann, data) + def handle_bit(self, miso, mosi, sck, cs): + # If this is the first bit, save its sample number. + if self.bitcount == 0: + self.startsample = self.samplenum + if self.have_cs: + active_low = (self.options['cs_polarity'] == 'active-low') + deasserted = cs if active_low else not cs + if deasserted: + self.cs_was_deasserted_during_data_word = 1 + + ws = self.options['wordsize'] + + # Receive MOSI bit into our shift register. + if self.options['bitorder'] == 'msb-first': + self.mosidata |= mosi << (ws - 1 - self.bitcount) + else: + self.mosidata |= mosi << self.bitcount + + # Receive MISO bit into our shift register. + if self.options['bitorder'] == 'msb-first': + self.misodata |= miso << (ws - 1 - self.bitcount) + else: + self.misodata |= miso << self.bitcount + + self.bitcount += 1 + + # Continue to receive if not enough bits were received, yet. + if self.bitcount != ws: + return + + self.putpw(['DATA', self.mosidata, self.misodata]) + self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) + self.putw([1, ['%02X' % self.misodata]]) + self.putw([2, ['%02X' % self.mosidata]]) + + if self.cs_was_deasserted_during_data_word: + self.putw([3, ['CS# was deasserted during this data word!']]) + + # Reset decoder state. + self.mosidata = self.misodata = self.bitcount = 0 + + # Keep stats for summary. + self.bytesreceived += 1 + + def find_clk_edge(self, miso, mosi, sck, cs): + if self.have_cs and self.oldcs != cs: + # Send all CS# pin value changes. + self.put(self.samplenum, self.samplenum, self.out_proto, + ['CS-CHANGE', self.oldcs, cs]) + self.oldcs = cs + # Reset decoder state when CS# changes (and the CS# pin is used). + self.mosidata = self.misodata = self.bitcount= 0 + + # Ignore sample if the clock pin hasn't changed. + if sck == self.oldsck: + return + + self.oldsck = sck + + # Sample data on rising/falling clock edge (depends on mode). + mode = spi_mode[self.options['cpol'], self.options['cpha']] + if mode == 0 and sck == 0: # Sample on rising clock edge + return + elif mode == 1 and sck == 1: # Sample on falling clock edge + return + elif mode == 2 and sck == 1: # Sample on falling clock edge + return + elif mode == 3 and sck == 0: # Sample on rising clock edge + return + + # Found the correct clock edge, now get the SPI bit(s). + self.handle_bit(miso, mosi, sck, cs) + def decode(self, ss, es, data): # TODO: Either MISO or MOSI could be optional. CS# is optional. for (self.samplenum, pins) in data: @@ -99,71 +194,11 @@ class Decoder(srd.Decoder): if self.oldpins == pins: continue self.oldpins, (miso, mosi, sck, cs) = pins, pins + self.have_cs = (cs in (0, 1)) - if self.oldcs != cs: - # Send all CS# pin value changes. - self.put(self.samplenum, self.samplenum, self.out_proto, - ['CS-CHANGE', self.oldcs, cs]) - self.oldcs = cs - - # Ignore sample if the clock pin hasn't changed. - if sck == self.oldsck: - continue - - self.oldsck = sck - - # Sample data on rising/falling clock edge (depends on mode). - mode = spi_mode[self.options['cpol'], self.options['cpha']] - if mode == 0 and sck == 0: # Sample on rising clock edge - continue - elif mode == 1 and sck == 1: # Sample on falling clock edge - continue - elif mode == 2 and sck == 1: # Sample on falling clock edge - continue - elif mode == 3 and sck == 0: # Sample on rising clock edge - continue - - # If this is the first bit, save its sample number. - if self.bitcount == 0: - self.startsample = self.samplenum - active_low = (self.options['cs_polarity'] == 'active-low') - deasserted = cs if active_low else not cs - if deasserted: - self.cs_was_deasserted_during_data_word = 1 - - ws = self.options['wordsize'] - - # Receive MOSI bit into our shift register. - if self.options['bitorder'] == 'msb-first': - self.mosidata |= mosi << (ws - 1 - self.bitcount) + # State machine. + if self.state == 'IDLE': + self.find_clk_edge(miso, mosi, sck, cs) else: - self.mosidata |= mosi << self.bitcount - - # Receive MISO bit into our shift register. - if self.options['bitorder'] == 'msb-first': - self.misodata |= miso << (ws - 1 - self.bitcount) - else: - self.misodata |= miso << self.bitcount - - self.bitcount += 1 - - # Continue to receive if not enough bits were received, yet. - if self.bitcount != ws: - continue - - self.putpw(['DATA', self.mosidata, self.misodata]) - self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) - self.putw([1, ['%02X' % self.misodata]]) - self.putw([2, ['%02X' % self.mosidata]]) - - if self.cs_was_deasserted_during_data_word: - self.putw([3, ['CS# was deasserted during this data word!']]) - - # Reset decoder state. - self.mosidata = 0 - self.misodata = 0 - self.bitcount = 0 - - # Keep stats for summary. - self.bytesreceived += 1 + raise Exception('Invalid state: %s' % self.state)