X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=6a2b5faff082c7e2d1369d44009d321ac14ec82d;hp=d077ccac0c91af870debe62237f2edd323536ba1;hb=84c1c0b52820af2418186ac3ecf93a5c6373a22e;hpb=8e8096e8289d8c5a5adf75109e481fe734e629f8;ds=sidebyside

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index d077cca..6a2b5fa 100644
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -77,14 +77,17 @@ class Decoder(srd.Decoder):
         {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
         {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
     ]
-    options = {
-        'cs_polarity': ['CS# polarity', 'active-low'],
-        'cpol': ['Clock polarity', 0],
-        'cpha': ['Clock phase', 0],
-        'bitorder': ['Bit order within the SPI data', 'msb-first'],
-        'wordsize': ['Word size of SPI data', 8], # 1-64?
-        'format': ['Data format', 'hex'],
-    }
+    options = (
+        {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low',
+            'values': ('active-low', 'active-high')},
+        {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0,
+            'values': (0, 1)},
+        {'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
+            'values': (0, 1)},
+        {'id': 'bitorder', 'desc': 'Bit order within the SPI data',
+            'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
+        {'id': 'wordsize', 'desc': 'Word size of SPI data', 'default': 8},
+    )
     annotations = [
         ['miso-data', 'MISO data'],
         ['mosi-data', 'MOSI data'],
@@ -125,9 +128,6 @@ class Decoder(srd.Decoder):
         self.out_bitrate = self.register(srd.OUTPUT_META,
                 meta=(int, 'Bitrate', 'Bitrate during transfers'))
 
-    def putpw(self, data):
-        self.put(self.startsample, self.samplenum, self.out_python, data)
-
     def putw(self, data):
         self.put(self.startsample, self.samplenum, self.out_ann, data)
 
@@ -137,8 +137,14 @@ class Decoder(srd.Decoder):
         si = self.mosidata if self.have_mosi else None
         so_bits = self.misobits if self.have_miso else None
         si_bits = self.mosibits if self.have_mosi else None
-        self.putpw(['BITS', si_bits, so_bits])
-        self.putpw(['DATA', si, so])
+
+        if self.have_miso:
+            ss, es = self.misobits[-1][1], self.misobits[0][2]
+        if self.have_mosi:
+            ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+
+        self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
+        self.put(ss, es, self.out_python, ['DATA', si, so])
 
         # Bit annotations.
         if self.have_miso:
@@ -150,10 +156,8 @@ class Decoder(srd.Decoder):
 
         # Dataword annotations.
         if self.have_miso:
-            ss, es = self.misobits[-1][1], self.misobits[0][2]
             self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
         if self.have_mosi:
-            ss, es = self.mosibits[-1][1], self.mosibits[0][2]
             self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
 
     def reset_decoder_state(self):