X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=6a2b5faff082c7e2d1369d44009d321ac14ec82d;hp=03a45da3b088575b473e27b4f751c1b1ba6588b7;hb=84c1c0b52820af2418186ac3ecf93a5c6373a22e;hpb=06b52ebb5fe7c09890dee02aa653578c2faf5a65 diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 03a45da..6a2b5fa 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -32,12 +32,18 @@ Commands: The data is _usually_ 8 bits (but can also be fewer or more bits). Both data items are Python numbers (not strings), or None if the respective probe was not supplied. + - 'BITS': / contain a list of bit values in this MISO/MOSI data + item, and for each of those also their respective start-/endsample numbers. - 'CS CHANGE': is the old CS# pin value, is the new value. Both data items are Python numbers (0/1), not strings. Examples: ['CS-CHANGE', 1, 0] ['DATA', 0xff, 0x3a] + ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], + [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]], + [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88], + [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]] ['DATA', 0x65, 0x00] ['DATA', 0xa8, None] ['DATA', None, 0x55] @@ -64,48 +70,52 @@ class Decoder(srd.Decoder): inputs = ['logic'] outputs = ['spi'] probes = [ - {'id': 'clk', 'name': 'CLK', 'desc': 'SPI clock line'}, + {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, ] optional_probes = [ - {'id': 'miso', 'name': 'MISO', - 'desc': 'SPI MISO line (master in, slave out)'}, - {'id': 'mosi', 'name': 'MOSI', - 'desc': 'SPI MOSI line (master out, slave in)'}, - {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, + {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'}, + {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'}, + {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'}, ] - options = { - 'cs_polarity': ['CS# polarity', 'active-low'], - 'cpol': ['Clock polarity', 0], - 'cpha': ['Clock phase', 0], - 'bitorder': ['Bit order within the SPI data', 'msb-first'], - 'wordsize': ['Word size of SPI data', 8], # 1-64? - 'format': ['Data format', 'hex'], - } + options = ( + {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low', + 'values': ('active-low', 'active-high')}, + {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0, + 'values': (0, 1)}, + {'id': 'cpha', 'desc': 'Clock phase', 'default': 0, + 'values': (0, 1)}, + {'id': 'bitorder', 'desc': 'Bit order within the SPI data', + 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')}, + {'id': 'wordsize', 'desc': 'Word size of SPI data', 'default': 8}, + ) annotations = [ - ['miso-data', 'MISO SPI data'], - ['mosi-data', 'MOSI SPI data'], + ['miso-data', 'MISO data'], + ['mosi-data', 'MOSI data'], + ['miso-bits', 'MISO bits'], + ['mosi-bits', 'MOSI bits'], ['warnings', 'Human-readable warnings'], ] annotation_rows = ( - ('miso', 'MISO', (0,)), - ('mosi', 'MOSI', (1,)), - ('other', 'Other', (2,)), + ('miso-data', 'MISO data', (0,)), + ('miso-bits', 'MISO bits', (2,)), + ('mosi-data', 'MOSI data', (1,)), + ('mosi-bits', 'MOSI bits', (3,)), + ('other', 'Other', (4,)), ) def __init__(self): self.samplerate = None self.oldclk = 1 self.bitcount = 0 - self.mosidata = 0 - self.misodata = 0 + self.misodata = self.mosidata = 0 + self.misobits = [] + self.mosibits = [] self.startsample = -1 self.samplenum = -1 - self.cs_was_deasserted_during_data_word = 0 + self.cs_was_deasserted = False self.oldcs = -1 self.oldpins = None - self.have_cs = None - self.have_miso = None - self.have_mosi = None + self.have_cs = self.have_miso = self.have_mosi = None self.state = 'IDLE' def metadata(self, key, value): @@ -118,24 +128,65 @@ class Decoder(srd.Decoder): self.out_bitrate = self.register(srd.OUTPUT_META, meta=(int, 'Bitrate', 'Bitrate during transfers')) - def putpw(self, data): - self.put(self.startsample, self.samplenum, self.out_python, data) - def putw(self, data): self.put(self.startsample, self.samplenum, self.out_ann, data) + def putdata(self): + # Pass MISO and MOSI bits and then data to the next PD up the stack. + so = self.misodata if self.have_miso else None + si = self.mosidata if self.have_mosi else None + so_bits = self.misobits if self.have_miso else None + si_bits = self.mosibits if self.have_mosi else None + + if self.have_miso: + ss, es = self.misobits[-1][1], self.misobits[0][2] + if self.have_mosi: + ss, es = self.mosibits[-1][1], self.mosibits[0][2] + + self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits]) + self.put(ss, es, self.out_python, ['DATA', si, so]) + + # Bit annotations. + if self.have_miso: + for bit in self.misobits: + self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]]) + if self.have_mosi: + for bit in self.mosibits: + self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]]) + + # Dataword annotations. + if self.have_miso: + self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]]) + if self.have_mosi: + self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]]) + + def reset_decoder_state(self): + self.misodata = 0 if self.have_miso else None + self.mosidata = 0 if self.have_mosi else None + self.misobits = [] if self.have_miso else None + self.mosibits = [] if self.have_mosi else None + self.bitcount = 0 + def handle_bit(self, miso, mosi, clk, cs): - # If this is the first bit, save its sample number. + # If this is the first bit of a dataword, save its sample number. if self.bitcount == 0: self.startsample = self.samplenum + self.cs_was_deasserted = False if self.have_cs: active_low = (self.options['cs_polarity'] == 'active-low') - deasserted = cs if active_low else not cs + deasserted = (cs == 1) if active_low else (cs == 0) if deasserted: - self.cs_was_deasserted_during_data_word = 1 + self.cs_was_deasserted = True ws = self.options['wordsize'] + # Receive MISO bit into our shift register. + if self.have_miso: + if self.options['bitorder'] == 'msb-first': + self.misodata |= miso << (ws - 1 - self.bitcount) + else: + self.misodata |= miso << self.bitcount + # Receive MOSI bit into our shift register. if self.have_mosi: if self.options['bitorder'] == 'msb-first': @@ -143,12 +194,23 @@ class Decoder(srd.Decoder): else: self.mosidata |= mosi << self.bitcount - # Receive MISO bit into our shift register. + # Guesstimate the endsample for this bit (can be overridden below). + es = self.samplenum + if self.bitcount > 0: + if self.have_miso: + es += self.samplenum - self.misobits[0][1] + elif self.have_mosi: + es += self.samplenum - self.mosibits[0][1] + if self.have_miso: - if self.options['bitorder'] == 'msb-first': - self.misodata |= miso << (ws - 1 - self.bitcount) - else: - self.misodata |= miso << self.bitcount + self.misobits.insert(0, [miso, self.samplenum, es]) + if self.have_mosi: + self.mosibits.insert(0, [mosi, self.samplenum, es]) + + if self.bitcount > 0 and self.have_miso: + self.misobits[1][2] = self.samplenum + if self.bitcount > 0 and self.have_mosi: + self.mosibits[1][2] = self.samplenum self.bitcount += 1 @@ -156,30 +218,18 @@ class Decoder(srd.Decoder): if self.bitcount != ws: return - si = self.mosidata if self.have_mosi else None - so = self.misodata if self.have_miso else None - - # Pass MOSI and MISO to the next PD up the stack. - self.putpw(['DATA', si, so]) - - # Annotations. - if self.have_miso: - self.putw([0, ['%02X' % self.misodata]]) - if self.have_mosi: - self.putw([1, ['%02X' % self.mosidata]]) + self.putdata() # Meta bitrate. - elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1) + elapsed = 1 / float(self.samplerate) + elapsed *= (self.samplenum - self.startsample + 1) bitrate = int(1 / elapsed * self.options['wordsize']) self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) - if self.have_cs and self.cs_was_deasserted_during_data_word: - self.putw([2, ['CS# was deasserted during this data word!']]) + if self.have_cs and self.cs_was_deasserted: + self.putw([4, ['CS# was deasserted during this data word!']]) - # Reset decoder state. - self.misodata = 0 if self.have_miso else None - self.mosidata = 0 if self.have_mosi else None - self.bitcount = 0 + self.reset_decoder_state() def find_clk_edge(self, miso, mosi, clk, cs): if self.have_cs and self.oldcs != cs: @@ -188,9 +238,7 @@ class Decoder(srd.Decoder): ['CS-CHANGE', self.oldcs, cs]) self.oldcs = cs # Reset decoder state when CS# changes (and the CS# pin is used). - self.misodata = 0 if self.have_miso else None - self.mosidata = 0 if self.have_mosi else None - self.bitcount = 0 + self.reset_decoder_state() # Ignore sample if the clock pin hasn't changed. if clk == self.oldclk: @@ -226,6 +274,10 @@ class Decoder(srd.Decoder): self.have_mosi = (mosi in (0, 1)) self.have_cs = (cs in (0, 1)) + # Either MISO or MOSI (but not both) can be omitted. + if not (self.have_miso or self.have_mosi): + raise Exception('Either MISO or MOSI (or both) pins required.') + # State machine. if self.state == 'IDLE': self.find_clk_edge(miso, mosi, clk, cs)