X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=679335e9489f06ead66c298944a2dea718c1b192;hp=0d35c0be8ef9deb741edff19d74824ec24b043ad;hb=d78e0beb6594de5dfd2a17d72f532a42f85ca55c;hpb=d482a2d39a9677a8c1ea91b945a2496b44caf642 diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 0d35c0b..679335e 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -42,8 +42,8 @@ Examples: ['DATA', 0xff, 0x3a] ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]], - [[0, 80, 82], [0, 83, 84], [1, 85, 86], [1, 87, 88], - [1, 89, 90], [0, 91, 92], [1, 93, 94], [0, 95, 96]]] + [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88], + [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]] ['DATA', 0x65, 0x00] ['DATA', 0xa8, None] ['DATA', None, 0x55] @@ -104,18 +104,15 @@ class Decoder(srd.Decoder): self.samplerate = None self.oldclk = 1 self.bitcount = 0 - self.mosidata = 0 - self.misodata = 0 - self.mosibits = [] + self.misodata = self.mosidata = 0 self.misobits = [] + self.mosibits = [] self.startsample = -1 self.samplenum = -1 - self.cs_was_deasserted_during_data_word = 0 + self.cs_was_deasserted = False self.oldcs = -1 self.oldpins = None - self.have_cs = None - self.have_miso = None - self.have_mosi = None + self.have_cs = self.have_miso = self.have_mosi = None self.state = 'IDLE' def metadata(self, key, value): @@ -134,11 +131,30 @@ class Decoder(srd.Decoder): def putw(self, data): self.put(self.startsample, self.samplenum, self.out_ann, data) - def putmisobit(self, i, data): - self.put(self.misobits[i][1], self.misobits[i][2], self.out_ann, data) + def putdata(self): + # Pass MISO and MOSI bits and then data to the next PD up the stack. + so = self.misodata if self.have_miso else None + si = self.mosidata if self.have_mosi else None + so_bits = self.misobits if self.have_miso else None + si_bits = self.mosibits if self.have_mosi else None + self.putpw(['BITS', si_bits, so_bits]) + self.putpw(['DATA', si, so]) - def putmosibit(self, i, data): - self.put(self.mosibits[i][1], self.mosibits[i][2], self.out_ann, data) + # Bit annotations. + if self.have_miso: + for bit in self.misobits: + self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]]) + if self.have_mosi: + for bit in self.mosibits: + self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]]) + + # Dataword annotations. + if self.have_miso: + ss, es = self.misobits[-1][1], self.misobits[0][2] + self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]]) + if self.have_mosi: + ss, es = self.mosibits[-1][1], self.mosibits[0][2] + self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]]) def reset_decoder_state(self): self.misodata = 0 if self.have_miso else None @@ -151,14 +167,22 @@ class Decoder(srd.Decoder): # If this is the first bit of a dataword, save its sample number. if self.bitcount == 0: self.startsample = self.samplenum + self.cs_was_deasserted = False if self.have_cs: active_low = (self.options['cs_polarity'] == 'active-low') - deasserted = cs if active_low else not cs + deasserted = (cs == 1) if active_low else (cs == 0) if deasserted: - self.cs_was_deasserted_during_data_word = 1 + self.cs_was_deasserted = True ws = self.options['wordsize'] + # Receive MISO bit into our shift register. + if self.have_miso: + if self.options['bitorder'] == 'msb-first': + self.misodata |= miso << (ws - 1 - self.bitcount) + else: + self.misodata |= miso << self.bitcount + # Receive MOSI bit into our shift register. if self.have_mosi: if self.options['bitorder'] == 'msb-first': @@ -166,24 +190,20 @@ class Decoder(srd.Decoder): else: self.mosidata |= mosi << self.bitcount - # Receive MISO bit into our shift register. - if self.have_miso: - if self.options['bitorder'] == 'msb-first': - self.misodata |= miso << (ws - 1 - self.bitcount) - else: - self.misodata |= miso << self.bitcount + # Guesstimate the endsample for this bit (can be overridden below). + es = self.samplenum + if self.bitcount > 0: + es += self.samplenum - self.misobits[0][1] if self.have_miso: - self.misobits.append([miso, self.samplenum, -1]) + self.misobits.insert(0, [miso, self.samplenum, es]) if self.have_mosi: - self.mosibits.append([mosi, self.samplenum, -1]) - if self.bitcount != 0: - if self.have_miso: - self.misobits[self.bitcount - 1][2] = self.samplenum - self.putmisobit(self.bitcount - 1, [3, ['%d' % miso]]) - if self.have_mosi: - self.mosibits[self.bitcount - 1][2] = self.samplenum - self.putmosibit(self.bitcount - 1, [2, ['%d' % mosi]]) + self.mosibits.insert(0, [mosi, self.samplenum, es]) + + if self.bitcount > 0 and self.have_miso: + self.misobits[1][2] = self.samplenum + if self.bitcount > 0 and self.have_mosi: + self.mosibits[1][2] = self.samplenum self.bitcount += 1 @@ -191,27 +211,15 @@ class Decoder(srd.Decoder): if self.bitcount != ws: return - si = self.mosidata if self.have_mosi else None - so = self.misodata if self.have_miso else None - si_bits = self.mosibits if self.have_mosi else None - so_bits = self.misobits if self.have_miso else None - - # Pass MOSI and MISO to the next PD up the stack. - self.putpw(['DATA', si, so]) - self.putpw(['BITS', si_bits, so_bits]) - - # Annotations. - if self.have_miso: - self.putw([0, ['%02X' % self.misodata]]) - if self.have_mosi: - self.putw([1, ['%02X' % self.mosidata]]) + self.putdata() # Meta bitrate. - elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1) + elapsed = 1 / float(self.samplerate) + elapsed *= (self.samplenum - self.startsample + 1) bitrate = int(1 / elapsed * self.options['wordsize']) self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) - if self.have_cs and self.cs_was_deasserted_during_data_word: + if self.have_cs and self.cs_was_deasserted: self.putw([4, ['CS# was deasserted during this data word!']]) self.reset_decoder_state() @@ -259,6 +267,10 @@ class Decoder(srd.Decoder): self.have_mosi = (mosi in (0, 1)) self.have_cs = (cs in (0, 1)) + # Either MISO or MOSI (but not both) can be omitted. + if not (self.have_miso or self.have_mosi): + raise Exception('Either MISO or MOSI (or both) pins required.') + # State machine. if self.state == 'IDLE': self.find_clk_edge(miso, mosi, clk, cs)