X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=2d971d31c4fb8657765489f4a6393eb5046f05f9;hp=b6c96bca82c1f18276587197b984bfefd6aa8118;hb=bbc100f764f523dbc63daed84be5011432685e9a;hpb=efa641735217e5425f93e69cbaddf70d75c7e9e4 diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index b6c96bc..2d971d3 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -2,7 +2,7 @@ ## This file is part of the libsigrokdecode project. ## ## Copyright (C) 2011 Gareth McMullin -## Copyright (C) 2012-2013 Uwe Hermann +## Copyright (C) 2012-2014 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -19,10 +19,37 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# SPI protocol decoder - import sigrokdecode as srd +''' +OUTPUT_PYTHON format: + +SPI packet: +[, , ] + +Commands: + - 'DATA': contains the MISO data, contains the MOSI data. + The data is _usually_ 8 bits (but can also be fewer or more bits). + Both data items are Python numbers (not strings), or None if the respective + probe was not supplied. + - 'BITS': / contain a list of bit values in this MISO/MOSI data + item, and for each of those also their respective start-/endsample numbers. + - 'CS CHANGE': is the old CS# pin value, is the new value. + Both data items are Python numbers (0/1), not strings. + +Examples: + ['CS-CHANGE', 1, 0] + ['DATA', 0xff, 0x3a] + ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], + [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]], + [[0, 80, 82], [0, 83, 84], [1, 85, 86], [1, 87, 88], + [1, 89, 90], [0, 91, 92], [1, 93, 94], [0, 95, 96]]] + ['DATA', 0x65, 0x00] + ['DATA', 0xa8, None] + ['DATA', None, 0x55] + ['CS-CHANGE', 0, 1] +''' + # Key: (CPOL, CPHA). Value: SPI mode. # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. @@ -43,14 +70,12 @@ class Decoder(srd.Decoder): inputs = ['logic'] outputs = ['spi'] probes = [ - {'id': 'miso', 'name': 'MISO', - 'desc': 'SPI MISO line (Master in, slave out)'}, - {'id': 'mosi', 'name': 'MOSI', - 'desc': 'SPI MOSI line (Master out, slave in)'}, - {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, + {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, ] optional_probes = [ - {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, + {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'}, + {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'}, + {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'}, ] options = { 'cs_polarity': ['CS# polarity', 'active-low'], @@ -61,40 +86,83 @@ class Decoder(srd.Decoder): 'format': ['Data format', 'hex'], } annotations = [ - ['MISO/MOSI data', 'MISO/MOSI SPI data'], - ['MISO data', 'MISO SPI data'], - ['MOSI data', 'MOSI SPI data'], - ['Warnings', 'Human-readable warnings'], + ['miso-data', 'MISO data'], + ['mosi-data', 'MOSI data'], + ['miso-bits', 'MISO bits'], + ['mosi-bits', 'MOSI bits'], + ['warnings', 'Human-readable warnings'], ] + annotation_rows = ( + ('miso-data', 'MISO data', (0,)), + ('miso-bits', 'MISO bits', (2,)), + ('mosi-data', 'MOSI data', (1,)), + ('mosi-bits', 'MOSI bits', (3,)), + ('other', 'Other', (4,)), + ) def __init__(self): - self.oldsck = 1 + self.samplerate = None + self.oldclk = 1 self.bitcount = 0 - self.mosidata = 0 - self.misodata = 0 - self.bytesreceived = 0 + self.misodata = self.mosidata = 0 + self.misobits = [] + self.mosibits = [] self.startsample = -1 self.samplenum = -1 self.cs_was_deasserted_during_data_word = 0 self.oldcs = -1 self.oldpins = None + self.have_cs = self.have_miso = self.have_mosi = None self.state = 'IDLE' - def start(self, metadata): - self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') - self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value - def report(self): - return 'SPI: %d bytes received' % self.bytesreceived + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) + self.out_bitrate = self.register(srd.OUTPUT_META, + meta=(int, 'Bitrate', 'Bitrate during transfers')) def putpw(self, data): - self.put(self.startsample, self.samplenum, self.out_proto, data) + self.put(self.startsample, self.samplenum, self.out_python, data) def putw(self, data): self.put(self.startsample, self.samplenum, self.out_ann, data) - def handle_bit(self, miso, mosi, sck, cs): - # If this is the first bit, save its sample number. + def putdata(self): + # Pass MISO and MOSI bits and then data to the next PD up the stack. + so = self.misodata if self.have_miso else None + si = self.mosidata if self.have_mosi else None + so_bits = self.misobits if self.have_miso else None + si_bits = self.mosibits if self.have_mosi else None + self.putpw(['BITS', si_bits, so_bits]) + self.putpw(['DATA', si, so]) + + # Bit annotations. + if self.have_miso: + for bit in self.misobits: + self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]]) + if self.have_mosi: + for bit in self.mosibits: + self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]]) + + # Dataword annotations. + if self.have_miso: + self.putw([0, ['%02X' % self.misodata]]) + if self.have_mosi: + self.putw([1, ['%02X' % self.mosidata]]) + + def reset_decoder_state(self): + self.misodata = 0 if self.have_miso else None + self.mosidata = 0 if self.have_mosi else None + self.misobits = [] if self.have_miso else None + self.mosibits = [] if self.have_mosi else None + self.bitcount = 0 + + def handle_bit(self, miso, mosi, clk, cs): + # If this is the first bit of a dataword, save its sample number. if self.bitcount == 0: self.startsample = self.samplenum if self.have_cs: @@ -105,17 +173,34 @@ class Decoder(srd.Decoder): ws = self.options['wordsize'] + # Receive MISO bit into our shift register. + if self.have_miso: + if self.options['bitorder'] == 'msb-first': + self.misodata |= miso << (ws - 1 - self.bitcount) + else: + self.misodata |= miso << self.bitcount + # Receive MOSI bit into our shift register. - if self.options['bitorder'] == 'msb-first': - self.mosidata |= mosi << (ws - 1 - self.bitcount) - else: - self.mosidata |= mosi << self.bitcount + if self.have_mosi: + if self.options['bitorder'] == 'msb-first': + self.mosidata |= mosi << (ws - 1 - self.bitcount) + else: + self.mosidata |= mosi << self.bitcount - # Receive MISO bit into our shift register. - if self.options['bitorder'] == 'msb-first': - self.misodata |= miso << (ws - 1 - self.bitcount) - else: - self.misodata |= miso << self.bitcount + # Guesstimate the endsample for this bit (can be overridden later). + es = self.samplenum + if self.bitcount > 0: + es += self.samplenum - self.misobits[self.bitcount - 1][1] + + if self.have_miso: + self.misobits.append([miso, self.samplenum, es]) + if self.have_mosi: + self.mosibits.append([mosi, self.samplenum, es]) + + if self.bitcount > 0 and self.have_miso: + self.misobits[self.bitcount - 1][2] = self.samplenum + if self.bitcount > 0 and self.have_mosi: + self.mosibits[self.bitcount - 1][2] = self.samplenum self.bitcount += 1 @@ -123,62 +208,65 @@ class Decoder(srd.Decoder): if self.bitcount != ws: return - self.putpw(['DATA', self.mosidata, self.misodata]) - self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) - self.putw([1, ['%02X' % self.misodata]]) - self.putw([2, ['%02X' % self.mosidata]]) + self.putdata() - if self.cs_was_deasserted_during_data_word: - self.putw([3, ['CS# was deasserted during this data word!']]) + # Meta bitrate. + elapsed = 1 / float(self.samplerate) + elapsed *= (self.samplenum - self.startsample + 1) + bitrate = int(1 / elapsed * self.options['wordsize']) + self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) - # Reset decoder state. - self.mosidata = self.misodata = self.bitcount = 0 + if self.have_cs and self.cs_was_deasserted_during_data_word: + self.putw([4, ['CS# was deasserted during this data word!']]) - # Keep stats for summary. - self.bytesreceived += 1 + self.reset_decoder_state() - def find_clk_edge(self, miso, mosi, sck, cs): + def find_clk_edge(self, miso, mosi, clk, cs): if self.have_cs and self.oldcs != cs: # Send all CS# pin value changes. - self.put(self.samplenum, self.samplenum, self.out_proto, + self.put(self.samplenum, self.samplenum, self.out_python, ['CS-CHANGE', self.oldcs, cs]) self.oldcs = cs # Reset decoder state when CS# changes (and the CS# pin is used). - self.mosidata = self.misodata = self.bitcount= 0 + self.reset_decoder_state() # Ignore sample if the clock pin hasn't changed. - if sck == self.oldsck: + if clk == self.oldclk: return - self.oldsck = sck + self.oldclk = clk # Sample data on rising/falling clock edge (depends on mode). mode = spi_mode[self.options['cpol'], self.options['cpha']] - if mode == 0 and sck == 0: # Sample on rising clock edge + if mode == 0 and clk == 0: # Sample on rising clock edge return - elif mode == 1 and sck == 1: # Sample on falling clock edge + elif mode == 1 and clk == 1: # Sample on falling clock edge return - elif mode == 2 and sck == 1: # Sample on falling clock edge + elif mode == 2 and clk == 1: # Sample on falling clock edge return - elif mode == 3 and sck == 0: # Sample on rising clock edge + elif mode == 3 and clk == 0: # Sample on rising clock edge return # Found the correct clock edge, now get the SPI bit(s). - self.handle_bit(miso, mosi, sck, cs) + self.handle_bit(miso, mosi, clk, cs) def decode(self, ss, es, data): - # TODO: Either MISO or MOSI could be optional. CS# is optional. + if self.samplerate is None: + raise Exception("Cannot decode without samplerate.") + # Either MISO or MOSI can be omitted (but not both). CS# is optional. for (self.samplenum, pins) in data: # Ignore identical samples early on (for performance reasons). if self.oldpins == pins: continue - self.oldpins, (miso, mosi, sck, cs) = pins, pins + self.oldpins, (clk, miso, mosi, cs) = pins, pins + self.have_miso = (miso in (0, 1)) + self.have_mosi = (mosi in (0, 1)) self.have_cs = (cs in (0, 1)) # State machine. if self.state == 'IDLE': - self.find_clk_edge(miso, mosi, sck, cs) + self.find_clk_edge(miso, mosi, clk, cs) else: raise Exception('Invalid state: %s' % self.state)