X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=25a9f85f9c059b662fefd203f7e364fdd0edfbb2;hp=78b167abb45d81082905d818fbcd464e761bb3fb;hb=1c49e875623918f8893308307f487a1f551daec4;hpb=bb08f4b3608b7ed4c932ed2041b1f41a5c9a7fed diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 78b167a..25a9f85 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -24,26 +24,28 @@ import sigrokdecode as srd ''' OUTPUT_PYTHON format: -SPI packet: -[, , ] +Packet: +[, , ] -Commands: - - 'DATA': contains the MISO data, contains the MOSI data. +: + - 'DATA': contains the MOSI data, contains the MISO data. The data is _usually_ 8 bits (but can also be fewer or more bits). Both data items are Python numbers (not strings), or None if the respective - probe was not supplied. - - 'BITS': / contain a list of bit values in this MISO/MOSI data + channel was not supplied. + - 'BITS': / contain a list of bit values in this MOSI/MISO data item, and for each of those also their respective start-/endsample numbers. - 'CS CHANGE': is the old CS# pin value, is the new value. - Both data items are Python numbers (0/1), not strings. + Both data items are Python numbers (0/1), not strings. At the beginning of + the decoding a packet is generated with = -1 and being the + initial state of the CS# pin or -1 if the chip select pin is not supplied. Examples: ['CS-CHANGE', 1, 0] ['DATA', 0xff, 0x3a] ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]], - [[0, 80, 82], [0, 83, 84], [1, 85, 86], [1, 87, 88], - [1, 89, 90], [0, 91, 92], [1, 93, 94], [0, 95, 96]]] + [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88], + [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]] ['DATA', 0x65, 0x00] ['DATA', 0xa8, None] ['DATA', None, 0x55] @@ -60,8 +62,14 @@ spi_mode = { (1, 1): 3, # Mode 3 } +class SamplerateError(Exception): + pass + +class ChannelError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'spi' name = 'SPI' longname = 'Serial Peripheral Interface' @@ -69,29 +77,32 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['spi'] - probes = [ + channels = ( {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, - ] - optional_probes = [ + ) + optional_channels = ( {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'}, {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'}, {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'}, - ] - options = { - 'cs_polarity': ['CS# polarity', 'active-low'], - 'cpol': ['Clock polarity', 0], - 'cpha': ['Clock phase', 0], - 'bitorder': ['Bit order within the SPI data', 'msb-first'], - 'wordsize': ['Word size of SPI data', 8], # 1-64? - 'format': ['Data format', 'hex'], - } - annotations = [ - ['miso-data', 'MISO data'], - ['mosi-data', 'MOSI data'], - ['miso-bits', 'MISO bits'], - ['mosi-bits', 'MOSI bits'], - ['warnings', 'Human-readable warnings'], - ] + ) + options = ( + {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low', + 'values': ('active-low', 'active-high')}, + {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0, + 'values': (0, 1)}, + {'id': 'cpha', 'desc': 'Clock phase', 'default': 0, + 'values': (0, 1)}, + {'id': 'bitorder', 'desc': 'Bit order', + 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')}, + {'id': 'wordsize', 'desc': 'Word size', 'default': 8}, + ) + annotations = ( + ('miso-data', 'MISO data'), + ('mosi-data', 'MOSI data'), + ('miso-bits', 'MISO bits'), + ('mosi-bits', 'MOSI bits'), + ('warnings', 'Human-readable warnings'), + ) annotation_rows = ( ('miso-data', 'MISO data', (0,)), ('miso-bits', 'MISO bits', (2,)), @@ -107,13 +118,13 @@ class Decoder(srd.Decoder): self.misodata = self.mosidata = 0 self.misobits = [] self.mosibits = [] - self.startsample = -1 + self.ss_block = -1 self.samplenum = -1 self.cs_was_deasserted = False self.oldcs = -1 self.oldpins = None self.have_cs = self.have_miso = self.have_mosi = None - self.state = 'IDLE' + self.no_cs_notification = False def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: @@ -125,11 +136,8 @@ class Decoder(srd.Decoder): self.out_bitrate = self.register(srd.OUTPUT_META, meta=(int, 'Bitrate', 'Bitrate during transfers')) - def putpw(self, data): - self.put(self.startsample, self.samplenum, self.out_python, data) - def putw(self, data): - self.put(self.startsample, self.samplenum, self.out_ann, data) + self.put(self.ss_block, self.samplenum, self.out_ann, data) def putdata(self): # Pass MISO and MOSI bits and then data to the next PD up the stack. @@ -137,8 +145,14 @@ class Decoder(srd.Decoder): si = self.mosidata if self.have_mosi else None so_bits = self.misobits if self.have_miso else None si_bits = self.mosibits if self.have_mosi else None - self.putpw(['BITS', si_bits, so_bits]) - self.putpw(['DATA', si, so]) + + if self.have_miso: + ss, es = self.misobits[-1][1], self.misobits[0][2] + if self.have_mosi: + ss, es = self.mosibits[-1][1], self.mosibits[0][2] + + self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits]) + self.put(ss, es, self.out_python, ['DATA', si, so]) # Bit annotations. if self.have_miso: @@ -150,10 +164,8 @@ class Decoder(srd.Decoder): # Dataword annotations. if self.have_miso: - ss, es = self.misobits[0][1], self.misobits[-1][2] self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]]) if self.have_mosi: - ss, es = self.mosibits[0][1], self.mosibits[-1][2] self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]]) def reset_decoder_state(self): @@ -166,13 +178,11 @@ class Decoder(srd.Decoder): def handle_bit(self, miso, mosi, clk, cs): # If this is the first bit of a dataword, save its sample number. if self.bitcount == 0: - self.startsample = self.samplenum + self.ss_block = self.samplenum self.cs_was_deasserted = False if self.have_cs: active_low = (self.options['cs_polarity'] == 'active-low') - deasserted = (cs == 1) if active_low else (cs == 0) - if deasserted: - self.cs_was_deasserted = True + self.cs_was_deasserted = (cs == 1) if active_low else (cs == 0) ws = self.options['wordsize'] @@ -193,17 +203,20 @@ class Decoder(srd.Decoder): # Guesstimate the endsample for this bit (can be overridden below). es = self.samplenum if self.bitcount > 0: - es += self.samplenum - self.misobits[self.bitcount - 1][1] + if self.have_miso: + es += self.samplenum - self.misobits[0][1] + elif self.have_mosi: + es += self.samplenum - self.mosibits[0][1] if self.have_miso: - self.misobits.append([miso, self.samplenum, es]) + self.misobits.insert(0, [miso, self.samplenum, es]) if self.have_mosi: - self.mosibits.append([mosi, self.samplenum, es]) + self.mosibits.insert(0, [mosi, self.samplenum, es]) if self.bitcount > 0 and self.have_miso: - self.misobits[self.bitcount - 1][2] = self.samplenum + self.misobits[1][2] = self.samplenum if self.bitcount > 0 and self.have_mosi: - self.mosibits[self.bitcount - 1][2] = self.samplenum + self.mosibits[1][2] = self.samplenum self.bitcount += 1 @@ -215,9 +228,9 @@ class Decoder(srd.Decoder): # Meta bitrate. elapsed = 1 / float(self.samplerate) - elapsed *= (self.samplenum - self.startsample + 1) + elapsed *= (self.samplenum - self.ss_block + 1) bitrate = int(1 / elapsed * self.options['wordsize']) - self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) + self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate) if self.have_cs and self.cs_was_deasserted: self.putw([4, ['CS# was deasserted during this data word!']]) @@ -254,8 +267,8 @@ class Decoder(srd.Decoder): self.handle_bit(miso, mosi, clk, cs) def decode(self, ss, es, data): - if self.samplerate is None: - raise Exception("Cannot decode without samplerate.") + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') # Either MISO or MOSI can be omitted (but not both). CS# is optional. for (self.samplenum, pins) in data: @@ -269,11 +282,11 @@ class Decoder(srd.Decoder): # Either MISO or MOSI (but not both) can be omitted. if not (self.have_miso or self.have_mosi): - raise Exception('Either MISO or MOSI (or both) pins required.') + raise ChannelError('Either MISO or MOSI (or both) pins required.') - # State machine. - if self.state == 'IDLE': - self.find_clk_edge(miso, mosi, clk, cs) - else: - raise Exception('Invalid state: %s' % self.state) + # Tell stacked decoders that we don't have a CS# signal. + if not self.no_cs_notification and not self.have_cs: + self.put(0, 0, self.out_python, ['CS-CHANGE', -1, -1]) + self.no_cs_notification = True + self.find_clk_edge(miso, mosi, clk, cs)