X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=0d35c0be8ef9deb741edff19d74824ec24b043ad;hp=88487bb77f6ef0772403330fe1f27a0c12138bad;hb=d482a2d39a9677a8c1ea91b945a2496b44caf642;hpb=12549f1161748215072541ed9a9c8625da041131 diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 88487bb..0d35c0b 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -22,7 +22,7 @@ import sigrokdecode as srd ''' -Protocol output format: +OUTPUT_PYTHON format: SPI packet: [, , ] @@ -32,12 +32,18 @@ Commands: The data is _usually_ 8 bits (but can also be fewer or more bits). Both data items are Python numbers (not strings), or None if the respective probe was not supplied. + - 'BITS': / contain a list of bit values in this MISO/MOSI data + item, and for each of those also their respective start-/endsample numbers. - 'CS CHANGE': is the old CS# pin value, is the new value. Both data items are Python numbers (0/1), not strings. Examples: ['CS-CHANGE', 1, 0] ['DATA', 0xff, 0x3a] + ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], + [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]], + [[0, 80, 82], [0, 83, 84], [1, 85, 86], [1, 87, 88], + [1, 89, 90], [0, 91, 92], [1, 93, 94], [0, 95, 96]]] ['DATA', 0x65, 0x00] ['DATA', 0xa8, None] ['DATA', None, 0x55] @@ -64,14 +70,12 @@ class Decoder(srd.Decoder): inputs = ['logic'] outputs = ['spi'] probes = [ - {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, + {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, ] optional_probes = [ - {'id': 'miso', 'name': 'MISO', - 'desc': 'SPI MISO line (master in, slave out)'}, - {'id': 'mosi', 'name': 'MOSI', - 'desc': 'SPI MOSI line (master out, slave in)'}, - {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, + {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'}, + {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'}, + {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'}, ] options = { 'cs_polarity': ['CS# polarity', 'active-low'], @@ -82,17 +86,28 @@ class Decoder(srd.Decoder): 'format': ['Data format', 'hex'], } annotations = [ - ['miso-data', 'MISO SPI data'], - ['mosi-data', 'MOSI SPI data'], + ['miso-data', 'MISO data'], + ['mosi-data', 'MOSI data'], + ['miso-bits', 'MISO bits'], + ['mosi-bits', 'MOSI bits'], ['warnings', 'Human-readable warnings'], ] + annotation_rows = ( + ('miso-data', 'MISO data', (0,)), + ('miso-bits', 'MISO bits', (2,)), + ('mosi-data', 'MOSI data', (1,)), + ('mosi-bits', 'MOSI bits', (3,)), + ('other', 'Other', (4,)), + ) def __init__(self): self.samplerate = None - self.oldsck = 1 + self.oldclk = 1 self.bitcount = 0 self.mosidata = 0 self.misodata = 0 + self.mosibits = [] + self.misobits = [] self.startsample = -1 self.samplenum = -1 self.cs_was_deasserted_during_data_word = 0 @@ -108,19 +123,32 @@ class Decoder(srd.Decoder): self.samplerate = value def start(self): - self.out_proto = self.register(srd.OUTPUT_PYTHON) + self.out_python = self.register(srd.OUTPUT_PYTHON) self.out_ann = self.register(srd.OUTPUT_ANN) self.out_bitrate = self.register(srd.OUTPUT_META, meta=(int, 'Bitrate', 'Bitrate during transfers')) def putpw(self, data): - self.put(self.startsample, self.samplenum, self.out_proto, data) + self.put(self.startsample, self.samplenum, self.out_python, data) def putw(self, data): self.put(self.startsample, self.samplenum, self.out_ann, data) - def handle_bit(self, miso, mosi, sck, cs): - # If this is the first bit, save its sample number. + def putmisobit(self, i, data): + self.put(self.misobits[i][1], self.misobits[i][2], self.out_ann, data) + + def putmosibit(self, i, data): + self.put(self.mosibits[i][1], self.mosibits[i][2], self.out_ann, data) + + def reset_decoder_state(self): + self.misodata = 0 if self.have_miso else None + self.mosidata = 0 if self.have_mosi else None + self.misobits = [] if self.have_miso else None + self.mosibits = [] if self.have_mosi else None + self.bitcount = 0 + + def handle_bit(self, miso, mosi, clk, cs): + # If this is the first bit of a dataword, save its sample number. if self.bitcount == 0: self.startsample = self.samplenum if self.have_cs: @@ -145,6 +173,18 @@ class Decoder(srd.Decoder): else: self.misodata |= miso << self.bitcount + if self.have_miso: + self.misobits.append([miso, self.samplenum, -1]) + if self.have_mosi: + self.mosibits.append([mosi, self.samplenum, -1]) + if self.bitcount != 0: + if self.have_miso: + self.misobits[self.bitcount - 1][2] = self.samplenum + self.putmisobit(self.bitcount - 1, [3, ['%d' % miso]]) + if self.have_mosi: + self.mosibits[self.bitcount - 1][2] = self.samplenum + self.putmosibit(self.bitcount - 1, [2, ['%d' % mosi]]) + self.bitcount += 1 # Continue to receive if not enough bits were received, yet. @@ -153,9 +193,12 @@ class Decoder(srd.Decoder): si = self.mosidata if self.have_mosi else None so = self.misodata if self.have_miso else None + si_bits = self.mosibits if self.have_mosi else None + so_bits = self.misobits if self.have_miso else None # Pass MOSI and MISO to the next PD up the stack. self.putpw(['DATA', si, so]) + self.putpw(['BITS', si_bits, so_bits]) # Annotations. if self.have_miso: @@ -169,43 +212,38 @@ class Decoder(srd.Decoder): self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) if self.have_cs and self.cs_was_deasserted_during_data_word: - self.putw([2, ['CS# was deasserted during this data word!']]) + self.putw([4, ['CS# was deasserted during this data word!']]) - # Reset decoder state. - self.misodata = 0 if self.have_miso else None - self.mosidata = 0 if self.have_mosi else None - self.bitcount = 0 + self.reset_decoder_state() - def find_clk_edge(self, miso, mosi, sck, cs): + def find_clk_edge(self, miso, mosi, clk, cs): if self.have_cs and self.oldcs != cs: # Send all CS# pin value changes. - self.put(self.samplenum, self.samplenum, self.out_proto, + self.put(self.samplenum, self.samplenum, self.out_python, ['CS-CHANGE', self.oldcs, cs]) self.oldcs = cs # Reset decoder state when CS# changes (and the CS# pin is used). - self.misodata = 0 if self.have_miso else None - self.mosidata = 0 if self.have_mosi else None - self.bitcount = 0 + self.reset_decoder_state() # Ignore sample if the clock pin hasn't changed. - if sck == self.oldsck: + if clk == self.oldclk: return - self.oldsck = sck + self.oldclk = clk # Sample data on rising/falling clock edge (depends on mode). mode = spi_mode[self.options['cpol'], self.options['cpha']] - if mode == 0 and sck == 0: # Sample on rising clock edge + if mode == 0 and clk == 0: # Sample on rising clock edge return - elif mode == 1 and sck == 1: # Sample on falling clock edge + elif mode == 1 and clk == 1: # Sample on falling clock edge return - elif mode == 2 and sck == 1: # Sample on falling clock edge + elif mode == 2 and clk == 1: # Sample on falling clock edge return - elif mode == 3 and sck == 0: # Sample on rising clock edge + elif mode == 3 and clk == 0: # Sample on rising clock edge return # Found the correct clock edge, now get the SPI bit(s). - self.handle_bit(miso, mosi, sck, cs) + self.handle_bit(miso, mosi, clk, cs) def decode(self, ss, es, data): if self.samplerate is None: @@ -216,14 +254,14 @@ class Decoder(srd.Decoder): # Ignore identical samples early on (for performance reasons). if self.oldpins == pins: continue - self.oldpins, (sck, miso, mosi, cs) = pins, pins + self.oldpins, (clk, miso, mosi, cs) = pins, pins self.have_miso = (miso in (0, 1)) self.have_mosi = (mosi in (0, 1)) self.have_cs = (cs in (0, 1)) # State machine. if self.state == 'IDLE': - self.find_clk_edge(miso, mosi, sck, cs) + self.find_clk_edge(miso, mosi, clk, cs) else: raise Exception('Invalid state: %s' % self.state)