X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi.py;h=accf4c6e41c75dd6206d38697b37cb4347ee8800;hp=480174ee60ba8befe6ebdf1d9ab676240dfb0085;hb=3d3da57d7e7a7414e012e86dde32530e01b4dc45;hpb=c94c8c918152004e7bed50a50dcf7be233674b9d

diff --git a/decoders/spi.py b/decoders/spi.py
index 480174e..accf4c6 100644
--- a/decoders/spi.py
+++ b/decoders/spi.py
@@ -30,8 +30,8 @@ CPOL_0 = 0 # Clock is low when inactive
 CPOL_1 = 1 # Clock is high when inactive
 
 # Clock phase options
-CPHA_0 = 0 # Data is valid on the rising clock edge
-CPHA_1 = 1 # Data is valid on the falling clock edge
+CPHA_0 = 0 # Data is valid on the leading clock edge
+CPHA_1 = 1 # Data is valid on the trailing clock edge
 
 # Bit order options
 MSB_FIRST = 0
@@ -50,7 +50,7 @@ ANN_HEX = 0
 class Decoder(srd.Decoder):
     id = 'spi'
     name = 'SPI'
-    longname = 'Serial Peripheral Interface (SPI) bus'
+    longname = 'Serial Peripheral Interface'
     desc = '...desc...'
     longdesc = '...longdesc...'
     author = 'Gareth McMullin'
@@ -67,7 +67,7 @@ class Decoder(srd.Decoder):
         {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
     ]
     options = {
-        'cs_active_low': ['CS# active low', ACTIVE_LOW],
+        'cs_polarity': ['CS# polarity', ACTIVE_LOW],
         'cpol': ['Clock polarity', CPOL_0],
         'cpha': ['Clock phase', CPHA_0],
         'bitorder': ['Bit order within the SPI data', MSB_FIRST],
@@ -84,9 +84,10 @@ class Decoder(srd.Decoder):
         self.misodata = 0
         self.bytesreceived = 0
         self.samplenum = -1
+        self.cs_was_deasserted_during_data_word = 0
 
         # Set protocol decoder option defaults.
-        self.cs_active_low = Decoder.options['cs_active_low'][1]
+        self.cs_polarity = Decoder.options['cs_polarity'][1]
         self.cpol = Decoder.options['cpol'][1]
         self.cpha = Decoder.options['cpha'][1]
         self.bitorder = Decoder.options['bitorder'][1]
@@ -128,6 +129,9 @@ class Decoder(srd.Decoder):
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
                 self.start_sample = samplenum
+                deasserted = cs if (self.cs_polarity == ACTIVE_LOW) else not c
+                if deasserted:
+                    self.cs_was_deasserted_during_data_word = 1
 
             # Receive MOSI bit into our shift register.
             if self.bitorder == MSB_FIRST:
@@ -153,6 +157,11 @@ class Decoder(srd.Decoder):
                      [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
                      self.misodata)]])
 
+            if self.cs_was_deasserted_during_data_word:
+                self.put(self.start_sample, self.samplenum, self.out_ann,
+                         [ANN_HEX, ['WARNING: CS# was deasserted during this '
+                         'SPI data byte!']])
+
             # Reset decoder state.
             self.mosidata = 0
             self.misodata = 0