X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi.py;h=a363b5afba3c0f53838229435876d83c0450d2e2;hp=7b3d8abbb472d45586f25857d0836aa82ce0c04f;hb=1c8ac5bf07e0ded582234c9ef50ba10f042bae52;hpb=ad2dc0de10ac5c2c6c3aacff0b2835cd4dc22578;ds=sidebyside diff --git a/decoders/spi.py b/decoders/spi.py index 7b3d8ab..a363b5a 100644 --- a/decoders/spi.py +++ b/decoders/spi.py @@ -18,6 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +import sigrok + class Sample(): def __init__(self, data): self.data = data @@ -29,10 +31,11 @@ def sampleiter(data, unitsize): for i in range(0, len(data), unitsize): yield(Sample(data[i:i+unitsize])) -class Decoder(): - name = 'SPI Decoder' +class Decoder(sigrok.Decoder): + id = 'spi' + name = 'SPI' desc = '...desc...' - longname = '...longname...' + longname = 'Serial Peripheral Interface (SPI) bus' longdesc = '...longdesc...' author = 'Gareth McMullin' email = 'gareth@blacksphere.co.nz' @@ -43,25 +46,24 @@ class Decoder(): probes = {'sdata':0, 'sck':1} options = {} - def __init__(self, unitsize, **kwargs): - # Metadata comes in here, we don't care for now - #print kwargs - self.unitsize = unitsize - + def __init__(self): self.probes = Decoder.probes.copy() self.oldsck = True self.rxcount = 0 self.rxdata = 0 self.bytesreceived = 0 + def start(self, metadata): + self.unitsize = metadata['unitsize'] + def report(self): - return "SPI: %d bytes received" % self.bytesreceived + return 'SPI: %d bytes received' % self.bytesreceived def decode(self, data): # We should accept a list of samples and iterate... - for sample in sampleiter(data["data"], self.unitsize): + for sample in sampleiter(data['data'], self.unitsize): - sck = sample.probe(self.probes["sck"]) + sck = sample.probe(self.probes['sck']) # Sample SDATA on rising SCK if sck == self.oldsck: continue @@ -71,9 +73,9 @@ class Decoder(): # If this is first bit, save timestamp if self.rxcount == 0: - self.time = data["time"] + self.time = data['time'] # Receive bit into our shift register - sdata = sample.probe(self.probes["sdata"]) + sdata = sample.probe(self.probes['sdata']) if sdata: self.rxdata |= 1 << (7 - self.rxcount) self.rxcount += 1 @@ -81,35 +83,16 @@ class Decoder(): if self.rxcount != 8: continue # Received a byte, pass up to sigrok - outdata = {"time":self.time, - "duration":data["time"] + data["duration"] - self.time, - "data":self.rxdata, - "display":("%02X" % self.rxdata), - "type":"spi", + outdata = {'time':self.time, + 'duration':data['time'] + data['duration'] - self.time, + 'data':self.rxdata, + 'display':('%02X' % self.rxdata), + 'type':'spi', } - sigrok.put(outdata) + self.put(outdata) # Reset decoder state self.rxdata = 0 self.rxcount = 0 # Keep stats for summary self.bytesreceived += 1 -if __name__ == "__main__": - data = open("spi_dump.bin").read() - - # dummy class to keep Decoder happy for test - class Sigrok(): - def put(self, data): - print "\t", data - sigrok = Sigrok() - - dec = Decoder(driver='ols', unitsize=1, starttime=0) - dec.decode({"time":0, "duration":len(data), "data":data, "type":"logic"}) - - print dec.summary() -else: - import sigrok - -#Tested with: -# sigrok-cli -d 0:samplerate=1000000:rle=on --time=1s -p 1,2 -a spidec -