X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi.py;h=5b97cd410d8888cdac7fb9199fcceba3cbd47e70;hp=0b688c81006a9bad4e957a2fd7bdae5c957a05ae;hb=01329e88ee576eb511528e691ddee23998d2de21;hpb=74911b4c1f6d184dac878d94992d480af0564734 diff --git a/decoders/spi.py b/decoders/spi.py index 0b688c8..5b97cd4 100644 --- a/decoders/spi.py +++ b/decoders/spi.py @@ -2,6 +2,7 @@ ## This file is part of the sigrok project. ## ## Copyright (C) 2011 Gareth McMullin +## Copyright (C) 2012 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,99 +18,153 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -class Sample(): - def __init__(self, data): - self.data = data - def probe(self, probe): - s = ord(self.data[probe / 8]) & (1 << (probe % 8)) - return True if s else False - -def sampleiter(data, unitsize): - for i in range(0, len(data), unitsize): - yield(Sample(data[i:i+unitsize])) - -class Decoder(): - name = 'SPI Decoder' + +import sigrokdecode as srd + +# Chip-select options +ACTIVE_LOW = 0 +ACTIVE_HIGH = 1 + +# Clock polarity options +CPOL_0 = 0 # Clock is low when inactive +CPOL_1 = 1 # Clock is high when inactive + +# Clock phase options +CPHA_0 = 0 # Data is valid on the rising clock edge +CPHA_1 = 1 # Data is valid on the falling clock edge + +# Bit order options +MSB_FIRST = 0 +LSB_FIRST = 1 + +spi_mode = { + (0, 0): 0, # Mode 0 + (0, 1): 1, # Mode 1 + (1, 0): 2, # Mode 2 + (1, 1): 3, # Mode 3 +} + +# Annotation formats +ANN_HEX = 0 + +class Decoder(srd.Decoder): + id = 'spi' + name = 'SPI' + longname = 'Serial Peripheral Interface (SPI) bus' desc = '...desc...' - longname = '...longname...' longdesc = '...longdesc...' author = 'Gareth McMullin' email = 'gareth@blacksphere.co.nz' license = 'gplv2+' inputs = ['logic'] outputs = ['spi'] - # Probe names with a set of defaults - probes = {'sdata':0, 'sck':1} - options = {} - - def __init__(self, unitsize, **kwargs): - # Metadata comes in here, we don't care for now - #print kwargs - self.unitsize = unitsize - - self.probes = Decoder.probes - self.oldsck = True - self.rxcount = 0 - self.rxdata = 0 + probes = [ + {'id': 'mosi', 'name': 'MOSI', + 'desc': 'SPI MOSI line (Master out, slave in)'}, + {'id': 'miso', 'name': 'MISO', + 'desc': 'SPI MISO line (Master in, slave out)'}, + {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, + {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, + ] + options = { + 'cs_active_low': ['CS# active low', ACTIVE_LOW], + 'cpol': ['Clock polarity', CPOL_0], + 'cpha': ['Clock phase', CPHA_0], + 'bitorder': ['Bit order within the SPI data', MSB_FIRST], + 'wordsize': ['Word size of SPI data', 8], # 1-64? + } + annotations = [ + ['Hex', 'SPI data bytes in hex format'], + ] + + def __init__(self): + self.oldsck = 1 + self.bitcount = 0 + self.mosidata = 0 + self.misodata = 0 self.bytesreceived = 0 + self.samplenum = -1 + self.cs_was_deasserted_during_data_word = 0 + + # Set protocol decoder option defaults. + self.cs_active_low = Decoder.options['cs_active_low'][1] + self.cpol = Decoder.options['cpol'][1] + self.cpha = Decoder.options['cpha'][1] + self.bitorder = Decoder.options['bitorder'][1] + self.wordsize = Decoder.options['wordsize'][1] + + def start(self, metadata): + self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') + self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') def report(self): - return "SPI: %d bytes received" % self.bytesreceived + return 'SPI: %d bytes received' % self.bytesreceived - def decode(self, data): - # We should accept a list of samples and iterate... - for sample in sampleiter(data["data"], self.unitsize): + def decode(self, ss, es, data): + # HACK! At the moment the number of probes is not handled correctly. + # E.g. if an input file (-i foo.sr) has more than two probes enabled. + # for (samplenum, (mosi, sck, x, y, z, a)) in data: + # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: + for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: - sck = sample.probe(self.probes["sck"]) - # Sample SDATA on rising SCK + self.samplenum += 1 # FIXME + + # Ignore sample if the clock pin hasn't changed. if sck == self.oldsck: continue + self.oldsck = sck - if not sck: - continue - - # If this is first bit, save timestamp - if self.rxcount == 0: - self.time = data["time"] - # Receive bit into our shift register - sdata = sample.probe(self.probes["sdata"]) - if sdata: - self.rxdata |= 1 << (7 - self.rxcount) - self.rxcount += 1 - # Continue to receive if not a byte yet - if self.rxcount != 8: - continue - # Received a byte, pass up to sigrok - outdata = {"time":self.time, - "duration":data["time"] + data["duration"] - self.time, - "data":self.rxdata, - "display":("%02X" % self.rxdata), - "type":"spi", - } - sigrok.put(outdata) - # Reset decoder state - self.rxdata = 0 - self.rxcount = 0 - # Keep stats for summary - self.bytesreceived += 1 - -if __name__ == "__main__": - data = open("spi_dump.bin").read() - # dummy class to keep Decoder happy for test - class Sigrok(): - def put(self, data): - print "\t", data - sigrok = Sigrok() + # Sample data on rising/falling clock edge (depends on mode). + mode = spi_mode[self.cpol, self.cpha] + if mode == 0 and sck == 0: # Sample on rising clock edge + continue + elif mode == 1 and sck == 1: # Sample on falling clock edge + continue + elif mode == 2 and sck == 1: # Sample on falling clock edge + continue + elif mode == 3 and sck == 0: # Sample on rising clock edge + continue + + # If this is the first bit, save its sample number. + if self.bitcount == 0: + self.start_sample = samplenum + if cs: + self.cs_was_deasserted_during_data_word = 1 - dec = Decoder(driver='ols', unitsize=1, starttime=0) - dec.decode({"time":0, "duration":len(data), "data":data, "type":"logic"}) + # Receive MOSI bit into our shift register. + if self.bitorder == MSB_FIRST: + self.mosidata |= mosi << (self.wordsize - 1 - self.bitcount) + else: + self.mosidata |= mosi << self.bitcount - print dec.summary() -else: - import sigrok + # Receive MISO bit into our shift register. + if self.bitorder == MSB_FIRST: + self.misodata |= miso << (self.wordsize - 1 - self.bitcount) + else: + self.misodata |= miso << self.bitcount -#Tested with: -# sigrok-cli -d 0:samplerate=1000000:rle=on --time=1s -p 1,2 -a spidec + self.bitcount += 1 + # Continue to receive if not a byte yet. + if self.bitcount != self.wordsize: + continue + + self.put(self.start_sample, self.samplenum, self.out_proto, + ['data', self.mosidata, self.misodata]) + self.put(self.start_sample, self.samplenum, self.out_ann, + [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, + self.misodata)]]) + + if self.cs_was_deasserted_during_data_word: + self.put(self.start_sample, self.samplenum, self.out_ann, + [ANN_HEX, ['WARNING: CS# was deasserted!']]) + + # Reset decoder state. + self.mosidata = 0 + self.misodata = 0 + self.bitcount = 0 + + # Keep stats for summary. + self.bytesreceived += 1