X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi.py;h=457abb5bde2f962cdd2c325023944eb6e9017aa9;hp=eaf60ef38bdb27fd1f52b9edd87bdde2a44e9e26;hb=0db89774dee57db500f270985f73f3bb2dcdbb42;hpb=4917bb31c6a1e3e77418ac446650a6d9aa3e528b

diff --git a/decoders/spi.py b/decoders/spi.py
index eaf60ef..457abb5 100644
--- a/decoders/spi.py
+++ b/decoders/spi.py
@@ -2,6 +2,7 @@
 ## This file is part of the sigrok project.
 ##
 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -20,6 +21,25 @@
 
 import sigrokdecode as srd
 
+# Chip-select options
+ACTIVE_LOW = 0
+ACTIVE_HIGH = 1
+
+# Clock polarity options
+CPOL_0 = 0 # Clock is low when inactive
+CPOL_1 = 1 # Clock is high when inactive
+
+# Clock phase options
+CPHA_0 = 0 # Data is valid on the rising clock edge
+CPHA_1 = 1 # Data is valid on the falling clock edge
+
+# Bit order options
+MSB_FIRST = 0
+LSB_FIRST = 1
+
+# Annotation formats
+ANN_HEX = 0
+
 class Decoder(srd.Decoder):
     id = 'spi'
     name = 'SPI'
@@ -32,22 +52,41 @@ class Decoder(srd.Decoder):
     inputs = ['logic']
     outputs = ['spi']
     probes = [
-        {'id': 'sdata', 'name': 'DATA', 'desc': 'SPI data line (MISO or MOSI)'},
+        {'id': 'mosi', 'name': 'MOSI',
+         'desc': 'SPI MOSI line (Master out, slave in)'},
+        {'id': 'miso', 'name': 'MISO',
+         'desc': 'SPI MISO line (Master in, slave out)'},
         {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
+        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
     ]
-    options = {}
+    options = {
+        'cs_active_low': ['CS# active low', ACTIVE_LOW],
+        'clock_polarity': ['Clock polarity', CPOL_0],
+        'clock_phase': ['Clock phase', CPHA_0],
+        'bit_order': ['Bit order within the SPI data', MSB_FIRST],
+        'word_size': ['Word size of SPI data', 8], # 1-64?
+    }
     annotations = [
-        ['TODO', 'TODO'],
+        ['Hex', 'SPI data bytes in hex format'],
     ]
 
     def __init__(self):
         self.oldsck = 1
         self.bitcount = 0
         self.mosidata = 0
+        self.misodata = 0
         self.bytesreceived = 0
+        self.samplenum = -1
+
+        # Set protocol decoder option defaults.
+        self.cs_active_low = Decoder.options['cs_active_low'][1]
+        self.clock_polarity = Decoder.options['clock_polarity'][1]
+        self.clock_phase = Decoder.options['clock_phase'][1]
+        self.bit_order = Decoder.options['bit_order'][1]
+        self.word_size = Decoder.options['word_size'][1]
 
     def start(self, metadata):
-        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
+        self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
         self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
 
     def report(self):
@@ -56,24 +95,28 @@ class Decoder(srd.Decoder):
     def decode(self, ss, es, data):
         # HACK! At the moment the number of probes is not handled correctly.
         # E.g. if an input file (-i foo.sr) has more than two probes enabled.
-        # for (samplenum, (sdata, sck, x, y, z, a)) in data:
+        # for (samplenum, (mosi, sck, x, y, z, a)) in data:
         # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
-        for (samplenum, (cs, miso, sck, sdata, wp, hold)) in data:
+        for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
+
+            self.samplenum += 1 # FIXME
 
-            # Sample SDATA on rising SCK.
+            # Sample data on rising SCK edges.
             if sck == self.oldsck:
                 continue
             self.oldsck = sck
             if sck == 0:
                 continue
 
-            # If this is the first bit, save timestamp.
+            # If this is the first bit, save its sample number.
             if self.bitcount == 0:
-                self.time = samplenum
+                self.start_sample = samplenum
 
             # Receive bit into our shift register.
-            if sdata == 1:
+            if mosi == 1:
                 self.mosidata |= 1 << (7 - self.bitcount)
+            if miso == 1:
+                self.misodata |= 1 << (7 - self.bitcount)
 
             self.bitcount += 1
 
@@ -81,11 +124,15 @@ class Decoder(srd.Decoder):
             if self.bitcount != 8:
                 continue
 
-            # self.put(0, 0, self.out_proto, out_proto) # TODO
-            self.put(0, 0, self.out_ann, [0, ['0x%02x' % self.mosidata]])
+            self.put(self.start_sample, self.samplenum, self.out_proto,
+                     ['data', self.mosidata, self.misodata])
+            self.put(self.start_sample, self.samplenum, self.out_ann,
+                     [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
+                     self.misodata)]])
 
             # Reset decoder state.
             self.mosidata = 0
+            self.misodata = 0
             self.bitcount = 0
 
             # Keep stats for summary.