X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fsignature%2Fpd.py;h=946b2da7574e7fb4b01e0caeb0d584fa1dee1ff5;hp=a86878f21f3409aa49a15dbb4f3b3f4910d55b35;hb=e144452bcdd5f2abbe6b6f3da41ad64f67e39def;hpb=112a2644fdadf17e077a84f63dbbccc87e649a0f

diff --git a/decoders/signature/pd.py b/decoders/signature/pd.py
index a86878f..946b2da 100644
--- a/decoders/signature/pd.py
+++ b/decoders/signature/pd.py
@@ -46,39 +46,42 @@ class Decoder(srd.Decoder):
     name = 'Signature'
     longname = 'Signature analysis'
     desc = 'Annotate signature of logic patterns.'
-    license = 'gplv3+'
+    license = 'gplv2+'
     inputs = ['logic']
     outputs = []
     tags = ['Debug/trace', 'Util', 'Encoding']
     channels = (
-        dict(id='start', name='START', desc='START channel'),
-        dict(id='stop', name='STOP', desc='STOP channel'),
-        dict(id='clk', name='CLOCK', desc='CLOCK channel'),
-        dict(id='data', name='DATA', desc='DATA channel')
+        {'id': 'start', 'name': 'START', 'desc': 'START channel'},
+        {'id': 'stop', 'name': 'STOP', 'desc': 'STOP channel'},
+        {'id': 'clk', 'name': 'CLOCK', 'desc': 'CLOCK channel'},
+        {'id': 'data', 'name': 'DATA', 'desc': 'DATA channel'},
     )
     options = (
-        dict(id='start_edge', desc='Edge-selection for START channel',
-             default='r', values=('r', 'f')),
-        dict(id='stop_edge', desc='Edge-selection for STOP channel',
-             default='r', values=('r', 'f')),
-        dict(id='clk_edge', desc='Edge-selection for CLOCK channel',
-             default='f', values=('r', 'f')),
-        dict(id='annbits', desc='Enable bit level annotation',
-             default='no', values=('yes', 'no'))
+        {'id': 'start_edge', 'desc': 'START edge polarity',
+            'default': 'rising', 'values': ('rising', 'falling')},
+        {'id': 'stop_edge', 'desc': 'STOP edge polarity',
+            'default': 'rising', 'values': ('rising', 'falling')},
+        {'id': 'clk_edge', 'desc': 'CLOCK edge polarity',
+            'default': 'falling', 'values': ('rising', 'falling')},
+        {'id': 'annbits', 'desc': 'Enable bit level annotations',
+            'default': 'no', 'values': ('yes', 'no')},
     )
     annotations = (
         ('bit0', 'Bit0'),
         ('bit1', 'Bit1'),
         ('start', 'START'),
         ('stop', 'STOP'),
-        ('sig', 'Sig')
+        ('signature', 'Signature')
     )
     annotation_rows = (
         ('bits', 'Bits', (0, 1, 2, 3)),
-        ('sig', 'Sig', (4,))
+        ('signatures', 'Signatures', (4,))
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         pass
 
     def start(self):
@@ -96,8 +99,8 @@ class Decoder(srd.Decoder):
 
     def decode(self):
         opt = self.options
-        start_edge_mode_rising = opt['start_edge'] == 'r'
-        stop_edge_mode_rising = opt['stop_edge'] == 'r'
+        start_edge_mode_rising = opt['start_edge'] == 'rising'
+        stop_edge_mode_rising = opt['stop_edge'] == 'rising'
         annbits = opt['annbits'] == 'yes'
         gate_is_open = False
         sample_start = None
@@ -132,7 +135,7 @@ class Decoder(srd.Decoder):
                         started = False
                     else:
                         self.putb(last_samplenum, [data, [str(data)]])
-                incoming = (bin(shiftreg & 0b0000_0010_1001_0001).count('1') + data) & 1
+                incoming = (bin(shiftreg & 0x0291).count('1') + data) & 1
                 shiftreg = (incoming << 15) | (shiftreg >> 1)
             prev_start = start
             prev_stop = stop