X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fsda2506%2Fpd.py;h=782fd837d29cd101b99cc7dbb2eb2274d47c3c32;hp=986312b34ae1f96baff0b256c968265782a4e359;hb=HEAD;hpb=d6d8a8a440ea2a81e6ddde33d16bc84d01cdb432

diff --git a/decoders/sda2506/pd.py b/decoders/sda2506/pd.py
index 986312b..6df5755 100644
--- a/decoders/sda2506/pd.py
+++ b/decoders/sda2506/pd.py
@@ -19,6 +19,9 @@
 
 import re
 import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
+
+Pin = SrdIntEnum.from_str('Pin', 'CLK DATA CE')
 
 ann_cmdbit, ann_databit, ann_cmd, ann_data, ann_warning = range(5)
 
@@ -30,7 +33,7 @@ class Decoder(srd.Decoder):
     desc = 'Serial nonvolatile 1-Kbit EEPROM.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['sda2506']
+    outputs = []
     tags = ['IC', 'Memory']
     channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
@@ -41,13 +44,13 @@ class Decoder(srd.Decoder):
         ('cmdbit', 'Command bit'),
         ('databit', 'Data bit'),
         ('cmd', 'Command'),
-        ('data', 'Data byte'),
-        ('warnings', 'Human-readable warnings'),
+        ('databyte', 'Data byte'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('bits', 'Bits', (ann_cmdbit, ann_databit)),
-        ('commands', 'Commands', (ann_cmd,)),
         ('data', 'Data', (ann_data,)),
+        ('commands', 'Commands', (ann_cmd,)),
         ('warnings', 'Warnings', (ann_warning,)),
     )
 
@@ -88,8 +91,8 @@ class Decoder(srd.Decoder):
 
     def decode(self):
         while True:
-            # Wait for CLK edge or CE edge.
-            clk, d, ce = self.wait([{0: 'e'}, {2: 'e'}])
+            # Wait for CLK edge or CE# edge.
+            clk, d, ce = self.wait([{Pin.CLK: 'e'}, {Pin.CE: 'e'}])
 
             if self.matched[0] and ce == 1 and clk == 1:
                 # Rising clk edge and command mode.