X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fsda2506%2Fpd.py;h=6df57554f69f0176facddd0d06682616bfcdfef7;hp=b860e648a5a17b935bfa5901457441bfe0abf3ad;hb=HEAD;hpb=811167552c54668f6407ac640f8eb47a32980dd8 diff --git a/decoders/sda2506/pd.py b/decoders/sda2506/pd.py index b860e64..6df5755 100644 --- a/decoders/sda2506/pd.py +++ b/decoders/sda2506/pd.py @@ -19,6 +19,9 @@ import re import sigrokdecode as srd +from common.srdhelper import SrdIntEnum + +Pin = SrdIntEnum.from_str('Pin', 'CLK DATA CE') ann_cmdbit, ann_databit, ann_cmd, ann_data, ann_warning = range(5) @@ -27,10 +30,11 @@ class Decoder(srd.Decoder): id = 'sda2506' name = 'SDA2506' longname = 'Siemens SDA 2506-5' - desc = 'Serial nonvolatile 1-Kbit EEPROM' + desc = 'Serial nonvolatile 1-Kbit EEPROM.' license = 'gplv2+' inputs = ['logic'] - outputs = ['sda2506'] + outputs = [] + tags = ['IC', 'Memory'] channels = ( {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, {'id': 'd', 'name': 'DATA', 'desc': 'Data'}, @@ -40,13 +44,13 @@ class Decoder(srd.Decoder): ('cmdbit', 'Command bit'), ('databit', 'Data bit'), ('cmd', 'Command'), - ('data', 'Data byte'), - ('warnings', 'Human-readable warnings'), + ('databyte', 'Data byte'), + ('warning', 'Warning'), ) annotation_rows = ( ('bits', 'Bits', (ann_cmdbit, ann_databit)), - ('commands', 'Commands', (ann_cmd,)), ('data', 'Data', (ann_data,)), + ('commands', 'Commands', (ann_cmd,)), ('warnings', 'Warnings', (ann_warning,)), ) @@ -87,8 +91,8 @@ class Decoder(srd.Decoder): def decode(self): while True: - # Wait for CLK edge or CE edge. - clk, d, ce = self.wait([{0: 'e'}, {2: 'e'}]) + # Wait for CLK edge or CE# edge. + clk, d, ce = self.wait([{Pin.CLK: 'e'}, {Pin.CE: 'e'}]) if self.matched[0] and ce == 1 and clk == 1: # Rising clk edge and command mode.