X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Frtc8564%2Fpd.py;h=ed55d4cf7b1b5cbbc11ead3a978737ed571cc070;hp=6f23e07e83c06706b2905cff1925b3649eb3d88f;hb=64134a4c84459474a1f1d767314f9a9ecf928539;hpb=001974848a862a7eeab7efc81cc0b21aec56464d diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py index 6f23e07..ed55d4c 100644 --- a/decoders/rtc8564/pd.py +++ b/decoders/rtc8564/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2012 Uwe Hermann +## Copyright (C) 2012-2014 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,8 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# Epson RTC-8564 JE/NB protocol decoder - import sigrokdecode as srd # Return the specified BCD number (max. 8 bits) as integer. @@ -37,14 +35,30 @@ class Decoder(srd.Decoder): outputs = ['rtc8564'] probes = [] optional_probes = [ - {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'TODO.'}, - {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'TODO.'}, - {'id': 'int', 'name': 'INT#', 'desc': 'TODO.'}, + {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'}, + {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'}, + {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'}, ] options = {} annotations = [ - ['Text', 'Human-readable text'], + ['reg-0x00', 'Register 0x00'], + ['reg-0x01', 'Register 0x01'], + ['reg-0x02', 'Register 0x02'], + ['reg-0x03', 'Register 0x03'], + ['reg-0x04', 'Register 0x04'], + ['reg-0x05', 'Register 0x05'], + ['reg-0x06', 'Register 0x06'], + ['reg-0x07', 'Register 0x07'], + ['reg-0x08', 'Register 0x08'], + ['read', 'Read date/time'], + ['write', 'Write date/time'], + ['bits', 'Bits'], ] + annotation_rows = ( + ('bits', 'Bits', (11,)), + ('regs', 'Registers', tuple(range(0, 8 + 1))), + ('date-time', 'Date/time', (9, 10)), + ) def __init__(self, **kwargs): self.state = 'IDLE' @@ -52,11 +66,12 @@ class Decoder(srd.Decoder): self.minutes = -1 self.seconds = -1 self.days = -1 + self.weekdays = -1 self.months = -1 self.years = -1 def start(self): - # self.out_proto = self.register(srd.OUTPUT_PYTHON) + # self.out_python = self.register(srd.OUTPUT_PYTHON) self.out_ann = self.register(srd.OUTPUT_ANN) def putx(self, data): @@ -88,37 +103,40 @@ class Decoder(srd.Decoder): ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\ 'event occurs\n' % (tie, s) - self.putx([0, [ann]]) + self.putx([1, [ann]]) - def handle_reg_0x02(self, b): # Seconds / Voltage-low flag - self.seconds = bcd2int(b & 0x7f) - self.putx([0, ['Seconds: %d' % self.seconds]]) + def handle_reg_0x02(self, b): # Seconds / Voltage-low bit + s = self.seconds = bcd2int(b & 0x7f) + self.putx([2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s]]) vl = 1 if (b & (1 << 7)) else 0 - self.putx([0, ['Voltage low (VL) bit: %d' % vl]]) + self.putx([11, ['Voltage low: %d' % vl, 'Volt low: %d' % vl, + 'VL: %d' % vl]]) def handle_reg_0x03(self, b): # Minutes - self.minutes = bcd2int(b & 0x7f) - self.putx([0, ['Minutes: %d' % self.minutes]]) + m = self.minutes = bcd2int(b & 0x7f) + self.putx([3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m]]) def handle_reg_0x04(self, b): # Hours - self.hours = bcd2int(b & 0x3f) - self.putx([0, ['Hours: %d' % self.hours]]) + h = self.hours = bcd2int(b & 0x3f) + self.putx([4, ['Hour: %d' % h, 'H: %d' % h]]) def handle_reg_0x05(self, b): # Days - self.days = bcd2int(b & 0x3f) - self.putx([0, ['Days: %d' % self.days]]) + d = self.days = bcd2int(b & 0x3f) + self.putx([5, ['Day: %d' % d, 'D: %d' % d]]) - def handle_reg_0x06(self, b): # Day counter - pass + def handle_reg_0x06(self, b): # Weekdays + w = self.weekdays = bcd2int(b & 0x07) + self.putx([6, ['Weekday: %d' % w, 'WD: %d' % w]]) - def handle_reg_0x07(self, b): # Months / century - # TODO: Handle century bit. - self.months = bcd2int(b & 0x1f) - self.putx([0, ['Months: %d' % self.months]]) + def handle_reg_0x07(self, b): # Months / century bit + m = self.months = bcd2int(b & 0x1f) + self.putx([7, ['Month: %d' % m, 'Mon: %d' % m]]) + c = 1 if (b & (1 << 7)) else 0 + self.putx([11, ['Century: %d' % c, 'Cent: %d' % c, 'C: %d' % c]]) def handle_reg_0x08(self, b): # Years - self.years = bcd2int(b & 0xff) - self.putx([0, ['Years: %d' % self.years]]) + y = self.years = bcd2int(b & 0xff) + self.putx([8, ['Year: %d' % y, 'Y: %d' % y]]) def handle_reg_0x09(self, b): # Alarm, minute pass @@ -182,7 +200,8 @@ class Decoder(srd.Decoder): d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months, self.years, self.hours, self.minutes, self.seconds) self.put(self.block_start_sample, es, self.out_ann, - [0, ['Written date/time: %s' % d]]) + [9, ['Write date/time: %s' % d, 'Write: %s' % d, + 'W: %s' % d]]) self.state = 'IDLE' else: pass # TODO @@ -204,7 +223,8 @@ class Decoder(srd.Decoder): d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months, self.years, self.hours, self.minutes, self.seconds) self.put(self.block_start_sample, es, self.out_ann, - [0, ['Read date/time: %s' % d]]) + [10, ['Read date/time: %s' % d, 'Read: %s' % d, + 'R: %s' % d]]) self.state = 'IDLE' else: pass # TODO?