X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Frtc8564%2Fpd.py;h=3c8404af78e5513049ef7034e603a5338a9c224b;hp=0aa7952f7ec1cadfd0580ac10346ecc8f6ea5ea6;hb=3161ab5a3569f88e6e9fadfd9d8e54f53620f104;hpb=a4289441eda34163f7e38f44367c4e888eb81eb1

diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py
index 0aa7952..3c8404a 100644
--- a/decoders/rtc8564/pd.py
+++ b/decoders/rtc8564/pd.py
@@ -52,7 +52,13 @@ class Decoder(srd.Decoder):
         ['reg-0x08', 'Register 0x08'],
         ['read', 'Read date/time'],
         ['write', 'Write date/time'],
+        ['bits', 'Bits'],
     ]
+    annotation_rows = (
+        ('bits', 'Bits', (11,)),
+        ('regs', 'Registers', tuple(range(0, 8 + 1))),
+        ('date-time', 'Date/time', (9, 10)),
+    )
 
     def __init__(self, **kwargs):
         self.state = 'IDLE'
@@ -102,7 +108,7 @@ class Decoder(srd.Decoder):
         self.seconds = bcd2int(b & 0x7f)
         self.putx([2, ['Seconds: %d' % self.seconds]])
         vl = 1 if (b & (1 << 7)) else 0
-        self.putx([2, ['Voltage low (VL) bit: %d' % vl]])
+        self.putx([11, ['Voltage low (VL) bit: %d' % vl]])
 
     def handle_reg_0x03(self, b): # Minutes
         self.minutes = bcd2int(b & 0x7f)