X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Frtc8564%2Fpd.py;h=2e9057316a97880fd11bf4759858be2b7d2d3a16;hp=6108c267239b4d488789ae4d42845ca83de34de9;hb=4539e9ca58966ce3c9cad4801b16c315e86ace01;hpb=780770f1295b7fdeb4481eb42623bad5da1e19a7 diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py index 6108c26..2e90573 100644 --- a/decoders/rtc8564/pd.py +++ b/decoders/rtc8564/pd.py @@ -14,18 +14,21 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd +from common.srdhelper import bcd2int -# Return the specified BCD number (max. 8 bits) as integer. -def bcd2int(b): - return (b & 0x0f) + ((b >> 4) * 10) +def reg_list(): + l = [] + for i in range(8 + 1): + l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i)) + + return tuple(l) class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'rtc8564' name = 'RTC-8564' longname = 'Epson RTC-8564 JE/NB' @@ -33,28 +36,22 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['i2c'] outputs = ['rtc8564'] - optional_probes = [ - {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'}, - {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'}, - {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'}, - ] - annotations = \ - [['reg-0x%02x' % i, 'Register 0x%02x' % i] for i in range(8 + 1)] + [ - ['read', 'Read date/time'], - ['write', 'Write date/time'], - ['bit-reserved', 'Reserved bit'], - ['bit-vl', 'VL bit'], - ['bit-century', 'Century bit'], - ['reg-read', 'Register read'], - ['reg-write', 'Register write'], - ] + annotations = reg_list() + ( + ('read', 'Read date/time'), + ('write', 'Write date/time'), + ('bit-reserved', 'Reserved bit'), + ('bit-vl', 'VL bit'), + ('bit-century', 'Century bit'), + ('reg-read', 'Register read'), + ('reg-write', 'Register write'), + ) annotation_rows = ( ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)), ('regs', 'Register access', (14, 15)), ('date-time', 'Date/time', (9, 10)), ) - def __init__(self, **kwargs): + def __init__(self): self.state = 'IDLE' self.hours = -1 self.minutes = -1 @@ -66,7 +63,6 @@ class Decoder(srd.Decoder): self.bits = [] def start(self): - # self.out_python = self.register(srd.OUTPUT_PYTHON) self.out_ann = self.register(srd.OUTPUT_ANN) def putx(self, data): @@ -189,7 +185,7 @@ class Decoder(srd.Decoder): if cmd != 'START': return self.state = 'GET SLAVE ADDR' - self.block_start_sample = ss + self.ss_block = ss elif self.state == 'GET SLAVE ADDR': # Wait for an address write operation. # TODO: We should only handle packets to the RTC slave (0xa2/0xa3). @@ -220,7 +216,7 @@ class Decoder(srd.Decoder): # TODO: Handle read/write of only parts of these items. d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months, self.years, self.hours, self.minutes, self.seconds) - self.put(self.block_start_sample, es, self.out_ann, + self.put(self.ss_block, es, self.out_ann, [9, ['Write date/time: %s' % d, 'Write: %s' % d, 'W: %s' % d]]) self.state = 'IDLE' @@ -246,12 +242,9 @@ class Decoder(srd.Decoder): elif cmd == 'STOP': d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months, self.years, self.hours, self.minutes, self.seconds) - self.put(self.block_start_sample, es, self.out_ann, + self.put(self.ss_block, es, self.out_ann, [10, ['Read date/time: %s' % d, 'Read: %s' % d, 'R: %s' % d]]) self.state = 'IDLE' else: pass # TODO? - else: - raise Exception('Invalid state: %s' % self.state) -