X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Frtc8564%2Fpd.py;h=1961c667f593fe8182b078b716ffd90999de15c8;hp=afc2fe02df9e8e0cbd78dfee7668b72310f17293;hb=09d09aceed72c7ca28023862c9049372dfef8d1d;hpb=c515eed7ef7a04a42b5b34abd308e08d6942835e

diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py
index afc2fe0..1961c66 100644
--- a/decoders/rtc8564/pd.py
+++ b/decoders/rtc8564/pd.py
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the libsigrokdecode project.
 ##
-## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -35,14 +35,34 @@ class Decoder(srd.Decoder):
     outputs = ['rtc8564']
     probes = []
     optional_probes = [
-        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'TODO.'},
-        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'TODO.'},
-        {'id': 'int', 'name': 'INT#', 'desc': 'TODO.'},
+        {'id': 'clkout', 'name': 'CLKOUT', 'desc': 'Clock output'},
+        {'id': 'clkoe', 'name': 'CLKOE', 'desc': 'Clock output enable'},
+        {'id': 'int', 'name': 'INT#', 'desc': 'Interrupt'},
     ]
     options = {}
     annotations = [
-        ['text', 'Human-readable text'],
+        ['reg-0x00', 'Register 0x00'],
+        ['reg-0x01', 'Register 0x01'],
+        ['reg-0x02', 'Register 0x02'],
+        ['reg-0x03', 'Register 0x03'],
+        ['reg-0x04', 'Register 0x04'],
+        ['reg-0x05', 'Register 0x05'],
+        ['reg-0x06', 'Register 0x06'],
+        ['reg-0x07', 'Register 0x07'],
+        ['reg-0x08', 'Register 0x08'],
+        ['read', 'Read date/time'],
+        ['write', 'Write date/time'],
+        ['bit-reserved', 'Reserved bit'],
+        ['bit-vl', 'VL bit'],
+        ['bit-century', 'Century bit'],
+        ['reg-read', 'Register read'],
+        ['reg-write', 'Register write'],
     ]
+    annotation_rows = (
+        ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
+        ('regs', 'Register access', (14, 15)),
+        ('date-time', 'Date/time', (9, 10)),
+    )
 
     def __init__(self, **kwargs):
         self.state = 'IDLE'
@@ -50,8 +70,10 @@ class Decoder(srd.Decoder):
         self.minutes = -1
         self.seconds = -1
         self.days = -1
+        self.weekdays = -1
         self.months = -1
         self.years = -1
+        self.bits = []
 
     def start(self):
         # self.out_python = self.register(srd.OUTPUT_PYTHON)
@@ -60,6 +82,13 @@ class Decoder(srd.Decoder):
     def putx(self, data):
         self.put(self.ss, self.es, self.out_ann, data)
 
+    def putd(self, bit1, bit2, data):
+        self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
+
+    def putr(self, bit):
+        self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
+                 [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
+
     def handle_reg_0x00(self, b): # Control register 1
         pass
 
@@ -86,37 +115,49 @@ class Decoder(srd.Decoder):
         ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
                'event occurs\n' % (tie, s)
 
-        self.putx([0, [ann]])
+        self.putx([1, [ann]])
 
-    def handle_reg_0x02(self, b): # Seconds / Voltage-low flag
-        self.seconds = bcd2int(b & 0x7f)
-        self.putx([0, ['Seconds: %d' % self.seconds]])
+    def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
         vl = 1 if (b & (1 << 7)) else 0
-        self.putx([0, ['Voltage low (VL) bit: %d' % vl]])
+        self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
+                        'VL: %d' % vl]])
+        s = self.seconds = bcd2int(b & 0x7f)
+        self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s]])
 
     def handle_reg_0x03(self, b): # Minutes
-        self.minutes = bcd2int(b & 0x7f)
-        self.putx([0, ['Minutes: %d' % self.minutes]])
+        self.putr(7)
+        m = self.minutes = bcd2int(b & 0x7f)
+        self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m]])
 
     def handle_reg_0x04(self, b): # Hours
-        self.hours = bcd2int(b & 0x3f)
-        self.putx([0, ['Hours: %d' % self.hours]])
+        self.putr(7)
+        self.putr(6)
+        h = self.hours = bcd2int(b & 0x3f)
+        self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h]])
 
     def handle_reg_0x05(self, b): # Days
-        self.days = bcd2int(b & 0x3f)
-        self.putx([0, ['Days: %d' % self.days]])
+        self.putr(7)
+        self.putr(6)
+        d = self.days = bcd2int(b & 0x3f)
+        self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d]])
 
-    def handle_reg_0x06(self, b): # Day counter
-        pass
+    def handle_reg_0x06(self, b): # Weekdays
+        for i in (7, 6, 5, 4, 3):
+            self.putr(i)
+        w = self.weekdays = bcd2int(b & 0x07)
+        self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w]])
 
-    def handle_reg_0x07(self, b): # Months / century
-        # TODO: Handle century bit.
-        self.months = bcd2int(b & 0x1f)
-        self.putx([0, ['Months: %d' % self.months]])
+    def handle_reg_0x07(self, b): # Months / century bit
+        c = 1 if (b & (1 << 7)) else 0
+        self.putd(7, 7, [13, ['Century: %d' % c, 'Cent: %d' % c, 'C: %d' % c]])
+        self.putr(6)
+        self.putr(5)
+        m = self.months = bcd2int(b & 0x1f)
+        self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m]])
 
     def handle_reg_0x08(self, b): # Years
-        self.years = bcd2int(b & 0xff)
-        self.putx([0, ['Years: %d' % self.years]])
+        y = self.years = bcd2int(b & 0xff)
+        self.putx([8, ['Year: %d' % y, 'Y: %d' % y]])
 
     def handle_reg_0x09(self, b): # Alarm, minute
         pass
@@ -142,6 +183,12 @@ class Decoder(srd.Decoder):
     def decode(self, ss, es, data):
         cmd, databyte = data
 
+        # Collect the 'BITS' packet, then return. The next packet is
+        # guaranteed to belong to these bits we just stored.
+        if cmd == 'BITS':
+            self.bits = databyte
+            return
+
         # Store the start/end samples of this I²C packet.
         self.ss, self.es = ss, es
 
@@ -171,6 +218,9 @@ class Decoder(srd.Decoder):
                 return
             # Otherwise: Get data bytes until a STOP condition occurs.
             if cmd == 'DATA WRITE':
+                r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
+                self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
+                                'WR %s' % s, 'WR', 'W']])
                 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                 handle_reg(databyte)
                 self.reg += 1
@@ -180,7 +230,8 @@ class Decoder(srd.Decoder):
                 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                     self.years, self.hours, self.minutes, self.seconds)
                 self.put(self.block_start_sample, es, self.out_ann,
-                         [0, ['Written date/time: %s' % d]])
+                         [9, ['Write date/time: %s' % d, 'Write: %s' % d,
+                              'W: %s' % d]])
                 self.state = 'IDLE'
             else:
                 pass # TODO
@@ -194,6 +245,9 @@ class Decoder(srd.Decoder):
                 pass # TODO
         elif self.state == 'READ RTC REGS2':
             if cmd == 'DATA READ':
+                r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
+                self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
+                                'RR %s' % s, 'RR', 'R']])
                 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                 handle_reg(databyte)
                 self.reg += 1
@@ -202,7 +256,8 @@ class Decoder(srd.Decoder):
                 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
                     self.years, self.hours, self.minutes, self.seconds)
                 self.put(self.block_start_sample, es, self.out_ann,
-                         [0, ['Read date/time: %s' % d]])
+                         [10, ['Read date/time: %s' % d, 'Read: %s' % d,
+                               'R: %s' % d]])
                 self.state = 'IDLE'
             else:
                 pass # TODO?