X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fps2%2Fpd.py;h=c5c9406d9f9c27ed1d85afcd2020146444f47965;hp=58c4d845bff3112254bef3b20175106ffb44fae8;hb=4c180223a8ae12feb7bc3601e07e848fb9cdb493;hpb=4539e9ca58966ce3c9cad4801b16c315e86ace01

diff --git a/decoders/ps2/pd.py b/decoders/ps2/pd.py
index 58c4d84..c5c9406 100644
--- a/decoders/ps2/pd.py
+++ b/decoders/ps2/pd.py
@@ -26,7 +26,7 @@ class Ann:
 Bit = namedtuple('Bit', 'val ss es')
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'ps2'
     name = 'PS/2'
     longname = 'PS/2'
@@ -34,6 +34,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['ps2']
+    tags = ['Logic', 'Bus']
     channels = (
         {'id': 'clk', 'name': 'Clock', 'desc': 'Clock line'},
         {'id': 'data', 'name': 'Data', 'desc': 'Data line'},
@@ -53,11 +54,11 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.bits = []
-        self.prev_pins = None
-        self.prev_clock = None
         self.samplenum = 0
-        self.clock_was_high = False
         self.bitcount = 0
 
     def start(self):
@@ -114,30 +115,8 @@ class Decoder(srd.Decoder):
 
         self.bits, self.bitcount = [], 0
 
-    def find_clk_edge(self, clock_pin, data_pin):
-        # Ignore sample if the clock pin hasn't changed.
-        if clock_pin == self.prev_clock:
-            return
-        self.prev_clock = clock_pin
-
-        # Sample on falling clock edge.
-        if clock_pin == 1:
-            return
-
-        # Found the correct clock edge, now get the bits.
-        self.handle_bits(data_pin)
-
-    def decode(self, ss, es, data):
-        for (self.samplenum, pins) in data:
-            clock_pin, data_pin = pins[0], pins[1]
-
-            # Ignore identical samples.
-            if self.prev_pins == pins:
-                continue
-            self.prev_pins = pins
-
-            if clock_pin == 0 and not self.clock_was_high:
-                continue
-            self.clock_was_high = True
-
-            self.find_clk_edge(clock_pin, data_pin)
+    def decode(self):
+        while True:
+            # Sample data bits on falling clock edge.
+            clock_pin, data_pin = self.wait({0: 'f'})
+            self.handle_bits(data_pin)