X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fparallel%2Fpd.py;h=a695ca6d403a45f2d2f81f8e1824cbf7d6f95a9d;hp=b2903d20e4b41425a4edc2163d990f095d1ee0e8;hb=35b380b1156434b73d4a976c68f5ab3604c8510a;hpb=c515eed7ef7a04a42b5b34abd308e08d6942835e diff --git a/decoders/parallel/pd.py b/decoders/parallel/pd.py index b2903d2..a695ca6 100644 --- a/decoders/parallel/pd.py +++ b/decoders/parallel/pd.py @@ -54,15 +54,15 @@ Packet: word is 7, and so on. ''' -def probe_list(num_probes): +def channel_list(num_channels): l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}] - for i in range(num_probes): + for i in range(num_channels): d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i} l.append(d) - return l + return tuple(l) class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'parallel' name = 'Parallel' longname = 'Parallel sync bus' @@ -70,18 +70,18 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['parallel'] - probes = [] - optional_probes = probe_list(8) - options = { - 'clock_edge': ['Clock edge to sample on', 'rising'], - 'wordsize': ['Word size of the data', 1], - 'endianness': ['Endianness of the data', 'little'], - 'format': ['Data format', 'hex'], - } - annotations = [ - ['items', 'Items'], - ['words', 'Words'], - ] + optional_channels = channel_list(8) + options = ( + {'id': 'clock_edge', 'desc': 'Clock edge to sample on', + 'default': 'rising', 'values': ('rising', 'falling')}, + {'id': 'wordsize', 'desc': 'Data wordsize', 'default': 1}, + {'id': 'endianness', 'desc': 'Data endianness', + 'default': 'little', 'values': ('little', 'big')}, + ) + annotations = ( + ('items', 'Items'), + ('words', 'Words'), + ) def __init__(self): self.oldclk = None @@ -92,7 +92,6 @@ class Decoder(srd.Decoder): self.oldpins = None self.ss_item = self.es_item = None self.first = True - self.state = 'IDLE' def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -123,7 +122,7 @@ class Decoder(srd.Decoder): self.items.append(item) self.itemcount += 1 - if self.first == True: + if self.first: # Save the start sample and item for later (no output yet). self.ss_item = self.samplenum self.first = False @@ -181,12 +180,7 @@ class Decoder(srd.Decoder): continue self.oldpins = pins - # State machine. - if self.state == 'IDLE': - if pins[0] not in (0, 1): - self.handle_bits(pins[1:]) - else: - self.find_clk_edge(pins[0], pins[1:]) + if pins[0] not in (0, 1): + self.handle_bits(pins[1:]) else: - raise Exception('Invalid state: %s' % self.state) - + self.find_clk_edge(pins[0], pins[1:])