X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fonewire_link%2F__init__.py;h=f55b998aaadeb2b313c31bf216b23c3df2471f64;hp=cb0347170958b385212fa5960d13bda3f844d234;hb=5484838563328e7d0533e6bdf5405829d24e7ca0;hpb=e7720d6c73eb981e57753c9028fa3e9019676c50

diff --git a/decoders/onewire_link/__init__.py b/decoders/onewire_link/__init__.py
index cb03471..f55b998 100644
--- a/decoders/onewire_link/__init__.py
+++ b/decoders/onewire_link/__init__.py
@@ -1,5 +1,5 @@
 ##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
 ##
 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
 ##
@@ -29,7 +29,7 @@ is layered:
  - Network layer (skip/search/match device ROM addresses)
  - Transport layer (transport data between 1-Wire master and device)
 
-Link layer protocol details:
+This protocol decoder handles the 1-Wire link layer.
 
 Sample rate:
 A sufficiently high samplerate is required to properly detect all the elements
@@ -65,27 +65,7 @@ configure the following timing values (number of samplerate periods):
 
 These options should be configured only on very rare cases and the user should
 read the decoder source code to understand them correctly.
-
-Protocol output format:
-TODO.
-
-Annotations:
-
-Link layer annotations show the following events:
-
- - NOTE/WARNING/ERROR
-   Possible samplerate related timing issues are reported.
- - Reset/presence true/false
-   The event is marked from the signal negative edge to the end of the reset
-   high period. It's also reported if there are any devices attached to the bus.
- - Bit 0/1
-   The event is marked from the signal negative edge to the end of the data
-   slot. The value of each received bit is also provided.
-
-TODO:
-- Check for protocol correctness, if events are timed inside prescribed limits.
-- Maybe add support for interrupts, check if this feature is deprecated.
 '''
 
-from .onewire_link import *
+from .pd import *