X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fmx25lxx05d%2Fmx25lxx05d.py;h=a5dab2ef39721f062855f36a0e0d39fe06af3378;hp=c6e950d9362ab4d07330def081824a9566de1710;hb=7cfbf663d2acd5c1d289e1eb6f4aafbf76dc169d;hpb=5ebb76fecc4ed07dd68a38dc55f3ba4ff34e7d70

diff --git a/decoders/mx25lxx05d/mx25lxx05d.py b/decoders/mx25lxx05d/mx25lxx05d.py
index c6e950d..a5dab2e 100644
--- a/decoders/mx25lxx05d/mx25lxx05d.py
+++ b/decoders/mx25lxx05d/mx25lxx05d.py
@@ -93,6 +93,31 @@ device_name = {
     0x16: 'MX25L6405D',
 }
 
+def decode_status_reg(data):
+    # TODO: Additional per-bit(s) self.put() calls with correct start/end.
+
+    # Bits[0:0]: WIP (write in progress)
+    s = 'W' if (data & (1 << 0)) else 'No w'
+    ret = '%srite operation in progress.\n' % s
+
+    # Bits[1:1]: WEL (write enable latch)
+    s = '' if (data & (1 << 1)) else 'not '
+    ret += 'Internal write enable latch is %sset.\n' % s
+
+    # Bits[5:2]: Block protect bits
+    # TODO: More detailed decoding (chip-dependent).
+    ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)
+
+    # Bits[6:6]: Continuously program mode (CP mode)
+    s = '' if (data & (1 << 6)) else 'not '
+    ret += 'Device is %sin continuously program mode (CP mode).\n' % s
+
+    # Bits[7:7]: SRWD (status register write disable)
+    s = '' if (data & (1 << 7)) else 'not '
+    ret += 'Status register writes are %sallowed.\n' % s
+
+    return ret
+
 class Decoder(srd.Decoder):
     api_version = 1
     id = 'mx25lxx05d'
@@ -168,16 +193,13 @@ class Decoder(srd.Decoder):
             self.start_sample = self.ss
             self.putx([0, ['Command: %s' % cmds[self.cmd]]])
         elif self.cmdstate in (2, 3, 4):
-            # Bytes 2/3/4: Master sends address of the sector to erase.
-            # Note: Assumes SPI data is 8 bits wide (it is for MX25Lxx05D).
-            # TODO: LSB-first of MSB-first?
-            self.addr <<= 8
-            self.addr |= mosi
-            self.putx([0, ['Address byte %d: 0x%02x' % (self.cmdstate - 1,
-                        miso)]]) # TODO: Count from 0 or 1?
+            # Bytes 2/3/4: Master sends sectror address (24bits, MSB-first).
+            self.addr |= (mosi << ((4 - self.cmdstate) * 8))
+            # self.putx([0, ['Sector address, byte %d: 0x%02x' % \
+            #                (4 - self.cmdstate, mosi)]])
 
         if self.cmdstate == 4:
-            d = 'Erase sector %d' % self.addr
+            d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
             self.put(self.start_sample, self.es, self.out_ann, [0, [d]])
             # TODO: Max. size depends on chip, check that too if possible.
             if self.addr % 4096 != 0:
@@ -238,7 +260,7 @@ class Decoder(srd.Decoder):
             # Bytes 2-x: Slave sends status register as long as master clocks.
             if self.cmdstate <= 3: # TODO: While CS# asserted.
                 self.putx([0, ['Status register: 0x%02x' % miso]])
-                # TODO: Decode status register bits.
+                self.putx([0, [decode_status_reg(miso)]])
 
             if self.cmdstate == 3: # TODO: If CS# got de-asserted.
                 self.state = IDLE