X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fmdio%2Fpd.py;h=8e970b1db5d2888cb835ad1b4febe4862a229802;hp=98e76e840776c81aa86a84c5943ca0983befe30e;hb=d6d8a8a440ea2a81e6ddde33d16bc84d01cdb432;hpb=d12e106fe565b2fd431c7306a1f38363960a33d4

diff --git a/decoders/mdio/pd.py b/decoders/mdio/pd.py
index 98e76e8..8e970b1 100644
--- a/decoders/mdio/pd.py
+++ b/decoders/mdio/pd.py
@@ -29,7 +29,7 @@
 import sigrokdecode as srd
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'mdio'
     name = 'MDIO'
     longname = 'Management Data Input/Output'
@@ -37,6 +37,7 @@ class Decoder(srd.Decoder):
     license = 'bsd'
     inputs = ['logic']
     outputs = ['mdio']
+    tags = ['Networking']
     channels = (
         {'id': 'mdc', 'name': 'MDC', 'desc': 'Clock'},
         {'id': 'mdio', 'name': 'MDIO', 'desc': 'Data'},
@@ -62,7 +63,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
-        self.last_mdc = 1
+        self.reset()
+
+    def reset(self):
         self.illegal_bus = 0
         self.samplenum = -1
         self.clause45_addr = -1 # Clause 45 is context sensitive.
@@ -77,6 +80,9 @@ class Decoder(srd.Decoder):
         if self.options['show_debug_bits'] == 'yes':
             self.put(ss, es, self.out_ann, [1, ['%d' % (self.bitcount - 1), '%d' % ((self.bitcount - 1) % 10)]])
 
+    def putff(self, data):
+        self.put(self.ss_frame_field, self.samplenum, self.out_ann, data)
+
     def putdata(self):
         self.put(self.ss_frame_field, self.mdiobits[0][2], self.out_ann,
                  [2, ['DATA: %04X' % self.data, 'DATA', 'D']])
@@ -90,7 +96,7 @@ class Decoder(srd.Decoder):
             if self.clause45 and self.clause45_addr != -1:
                 decoded_min += str.format('ADDR: %04X ' % self.clause45_addr)
             elif self.clause45:
-                decoded_min += str.format('ADDR: UKWN ' % self.clause45_addr)
+                decoded_min += str.format('ADDR: UKWN ')
 
             if self.clause45 and self.opcode > 1 \
             or (not self.clause45 and self.opcode):
@@ -194,8 +200,7 @@ class Decoder(srd.Decoder):
                 st = ['ST (Clause 45)', 'ST 45']
             else:
                 st = ['ST (Clause 22)', 'ST 22']
-            self.put(self.ss_frame_field, self.samplenum, self.out_ann,
-                     [2, st + ['ST', 'S']])
+            self.putff([2, st + ['ST', 'S']])
             self.ss_frame_field = self.samplenum
 
             if mdio:
@@ -225,11 +230,9 @@ class Decoder(srd.Decoder):
                     op = ['OP: READ', 'OP: R']
             else:
                 op = ['OP: READ', 'OP: R'] if self.opcode else ['OP: WRITE', 'OP: W']
-            self.put(self.ss_frame_field, self.samplenum, self.out_ann,
-                     [2, op + ['OP', 'O']])
+            self.putff([2, op + ['OP', 'O']])
             if self.op_invalid:
-                self.put(self.ss_frame_field, self.samplenum, self.out_ann,
-                         [4, ['OP %s' % self.op_invalid, 'OP', 'O']])
+                self.putff([4, ['OP %s' % self.op_invalid, 'OP', 'O']])
             self.ss_frame_field = self.samplenum
         self.portad_bits -= 1
         self.portad |= mdio << self.portad_bits
@@ -243,8 +246,7 @@ class Decoder(srd.Decoder):
                 prtad = ['PRTAD: %02d' % self.portad, 'PRT', 'P']
             else:
                 prtad = ['PHYAD: %02d' % self.portad, 'PHY', 'P']
-            self.put(self.ss_frame_field, self.samplenum, self.out_ann,
-                     [2, prtad])
+            self.putff([2, prtad])
             self.ss_frame_field = self.samplenum
         self.devad_bits -= 1
         self.devad |= mdio << self.devad_bits
@@ -258,8 +260,7 @@ class Decoder(srd.Decoder):
                 regad = ['DEVAD: %02d' % self.devad, 'DEV', 'D']
             else:
                 regad = ['REGAD: %02d' % self.devad, 'REG', 'R']
-            self.put(self.ss_frame_field, self.samplenum, self.out_ann,
-                     [2, regad])
+            self.putff([2, regad])
             self.ss_frame_field = self.samplenum
             if mdio != 1 and ((self.clause45 and self.opcode < 2)
             or (not self.clause45 and self.opcode == 0)):
@@ -275,11 +276,9 @@ class Decoder(srd.Decoder):
     def state_DATA(self, mdio):
         if self.data == -1:
             self.data = 0
-            self.put(self.ss_frame_field, self.samplenum, self.out_ann,
-                     [2, ['TA', 'T']])
+            self.putff([2, ['TA', 'T']])
             if self.ta_invalid:
-                self.put(self.ss_frame_field, self.samplenum, self.out_ann,
-                         [4, ['TA%s' % self.ta_invalid, 'TA', 'T']])
+                self.putff([4, ['TA%s' % self.ta_invalid, 'TA', 'T']])
             self.ss_frame_field = self.samplenum
         self.data_bits -= 1
         self.data |= mdio << self.data_bits
@@ -320,14 +319,8 @@ class Decoder(srd.Decoder):
 
         self.process_state(self.state, mdio)
 
-    def decode(self, ss, es, data):
-        for (self.samplenum, pins) in data:
-            # Ignore identical samples early on (for performance reasons).
-            if self.last_mdc == pins[0]:
-                continue
-            self.last_mdc = pins[0]
-            if pins[0] == 0: # Check for rising edge.
-                continue
-
-            # Found the correct clock edge, now get/handle the bit(s).
+    def decode(self):
+        while True:
+            # Process pin state upon rising MDC edge.
+            pins = self.wait({0: 'r'})
             self.handle_bit(pins[1])