X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Flpc%2Fpd.py;h=452e647118131428a5cebf42fcf22f0ab24f7858;hp=7da0dd8761d8d4d3af875ca1f96ea88e4027b1ea;hb=aad263bb83593a66d4a834b30acf8e8a2f1b5c4c;hpb=cded73ba6a9a2095d06e92912a7e6f6ccb22307e diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py index 7da0dd8..452e647 100644 --- a/decoders/lpc/pd.py +++ b/decoders/lpc/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2012 Uwe Hermann +## Copyright (C) 2012-2013 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,12 +14,9 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## -# LPC protocol decoder - import sigrokdecode as srd # ... @@ -98,7 +95,7 @@ fields = { } class Decoder(srd.Decoder): - api_version = 1 + api_version = 3 id = 'lpc' name = 'LPC' longname = 'Low-Pin-Count' @@ -106,33 +103,45 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['lpc'] - probes = [ - {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'}, - {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'}, - {'id': 'lclk', 'name': 'LCLK', 'desc': 'TODO'}, - {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'TODO'}, - {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'TODO'}, - {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'TODO'}, - {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'TODO'}, - ] - optional_probes = [ - {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'TODO'}, - {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'TODO'}, - {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'}, - {'id': 'lpme', 'name': 'LPME#', 'desc': 'TODO'}, - {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'TODO'}, - {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'TODO'}, - ] - options = {} - annotations = [ - ['Text', 'Human-readable text'], - ] - - def __init__(self, **kwargs): + channels = ( + {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'}, + {'id': 'lclk', 'name': 'LCLK', 'desc': 'Clock'}, + {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'Addr/control/data 0'}, + {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'Addr/control/data 1'}, + {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'Addr/control/data 2'}, + {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'Addr/control/data 3'}, + ) + optional_channels = ( + {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'}, + {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'Encoded DMA / bus master request'}, + {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'Serialized IRQ'}, + {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'Clock run'}, + {'id': 'lpme', 'name': 'LPME#', 'desc': 'LPC power management event'}, + {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'Power down'}, + {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'System Management Interrupt'}, + ) + annotations = ( + ('warnings', 'Warnings'), + ('start', 'Start'), + ('cycle-type', 'Cycle-type/direction'), + ('addr', 'Address'), + ('tar1', 'Turn-around cycle 1'), + ('sync', 'Sync'), + ('data', 'Data'), + ('tar2', 'Turn-around cycle 2'), + ) + annotation_rows = ( + ('data', 'Data', (1, 2, 3, 4, 5, 6, 7)), + ('warnings', 'Warnings', (0,)), + ) + + def __init__(self): + self.reset() + + def reset(self): self.state = 'IDLE' self.oldlclk = -1 self.samplenum = 0 - self.clocknum = 0 self.lad = -1 self.addr = 0 self.cur_nibble = 0 @@ -140,14 +149,14 @@ class Decoder(srd.Decoder): self.databyte = 0 self.tarcount = 0 self.synccount = 0 - self.oldpins = (-1, -1, -1, -1, -1, -1, -1) + self.oldpins = None + self.ss_block = self.es_block = None - def start(self, metadata): - # self.out_proto = self.add(srd.OUTPUT_PROTO, 'lpc') - self.out_ann = self.add(srd.OUTPUT_ANN, 'lpc') + def start(self): + self.out_ann = self.register(srd.OUTPUT_ANN) - def report(self): - pass + def putb(self, data): + self.put(self.ss_block, self.es_block, self.out_ann, data) def handle_get_start(self, lad, lad_bits, lframe): # LAD[3:0]: START field (1 clock cycle). @@ -156,15 +165,14 @@ class Decoder(srd.Decoder): # the peripherals must use. However, the host can keep LFRAME# asserted # multiple clocks, and we output all START fields that occur, even # though the peripherals are supposed to ignore all but the last one. - s = fields['START'][lad] - self.put(0, 0, self.out_ann, [0, [s]]) + self.es_block = self.samplenum + self.putb([1, [fields['START'][lad], 'START', 'St', 'S']]) + self.ss_block = self.samplenum # Output a warning if LAD[3:0] changes while LFRAME# is low. # TODO if (self.lad != -1 and self.lad != lad): - self.put(0, 0, self.out_ann, - [0, ['Warning: LAD[3:0] changed while ' - 'LFRAME# was asserted']]) + self.putb([0, ['LAD[3:0] changed while LFRAME# was asserted']]) # LFRAME# is asserted (low). Wait until it gets de-asserted again # (the host is allowed to keep it asserted multiple clocks). @@ -177,15 +185,15 @@ class Decoder(srd.Decoder): def handle_get_ct_dr(self, lad, lad_bits): # LAD[3:0]: Cycle type / direction field (1 clock cycle). - self.cycle_type = fields['CT_DR'][lad] + self.cycle_type = fields['CT_DR'].get(lad, 'Reserved / unknown') # TODO: Warning/error on invalid cycle types. - if self.cycle_type == 'Reserved': - self.put(0, 0, self.out_ann, - [0, ['Warning: Invalid cycle type (%s)' % lad_bits]]) + if 'Reserved' in self.cycle_type: + self.putb([0, ['Invalid cycle type (%s)' % lad_bits]]) - # ... - self.put(0, 0, self.out_ann, [0, ['Cycle type: %s' % self.cycle_type]]) + self.es_block = self.samplenum + self.putb([2, ['Cycle type: %s' % self.cycle_type]]) + self.ss_block = self.samplenum self.state = 'GET ADDR' self.addr = 0 @@ -212,8 +220,10 @@ class Decoder(srd.Decoder): self.cur_nibble += 1 return + self.es_block = self.samplenum s = 'Address: 0x%%0%dx' % addr_nibbles - self.put(0, 0, self.out_ann, [0, [s % self.addr]]) + self.putb([3, [s % self.addr]]) + self.ss_block = self.samplenum self.state = 'GET TAR' self.tar_count = 0 @@ -221,17 +231,17 @@ class Decoder(srd.Decoder): def handle_get_tar(self, lad, lad_bits): # LAD[3:0]: First TAR (turn-around) field (2 clock cycles). - self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s' - % (self.tarcount, lad_bits)]]) + self.es_block = self.samplenum + self.putb([4, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]]) + self.ss_block = self.samplenum # On the first TAR clock cycle LAD[3:0] is driven to 1111 by # either the host or peripheral. On the second clock cycle, # the host or peripheral tri-states LAD[3:0], but its value # should still be 1111, due to pull-ups on the LAD lines. if lad_bits != '1111': - self.put(0, 0, self.out_ann, - [0, ['Warning: TAR, cycle %d: %s (expected 1111)' - % (self.tarcount, lad_bits)]]) + self.putb([0, ['TAR, cycle %d: %s (expected 1111)' % \ + (self.tarcount, lad_bits)]]) if (self.tarcount != 1): self.tarcount += 1 @@ -244,15 +254,16 @@ class Decoder(srd.Decoder): # LAD[3:0]: SYNC field (1-n clock cycles). self.sync_val = lad_bits - self.cycle_type = fields['SYNC'][lad] + self.cycle_type = fields['SYNC'].get(lad, 'Reserved / unknown') # TODO: Warnings if reserved value are seen? - if self.cycle_type == 'Reserved': - self.put(0, 0, self.out_ann, [0, ['Warning: SYNC, cycle %d: %s ' - '(reserved value)' % (self.synccount, self.sync_val)]]) + if 'Reserved' in self.cycle_type: + self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \ + (self.synccount, self.sync_val)]]) - self.put(0, 0, self.out_ann, [0, ['SYNC, cycle %d: %s' - % (self.synccount, self.sync_val)]]) + self.es_block = self.samplenum + self.putb([5, ['SYNC, cycle %d: %s' % (self.synccount, self.sync_val)]]) + self.ss_block = self.samplenum # TODO @@ -274,7 +285,9 @@ class Decoder(srd.Decoder): self.cycle_count += 1 return - self.put(0, 0, self.out_ann, [0, ['DATA: 0x%02x' % self.databyte]]) + self.es_block = self.samplenum + self.putb([6, ['DATA: 0x%02x' % self.databyte]]) + self.ss_block = self.samplenum self.cycle_count = 0 self.state = 'GET TAR2' @@ -282,17 +295,17 @@ class Decoder(srd.Decoder): def handle_get_tar2(self, lad, lad_bits): # LAD[3:0]: Second TAR field (2 clock cycles). - self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s' - % (self.tarcount, lad_bits)]]) + self.es_block = self.samplenum + self.putb([7, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]]) + self.ss_block = self.samplenum # On the first TAR clock cycle LAD[3:0] is driven to 1111 by # either the host or peripheral. On the second clock cycle, # the host or peripheral tri-states LAD[3:0], but its value # should still be 1111, due to pull-ups on the LAD lines. if lad_bits != '1111': - self.put(0, 0, self.out_ann, - [0, ['Warning: TAR, cycle %d: %s (expected 1111)' - % (self.tarcount, lad_bits)]]) + self.putb([0, ['Warning: TAR, cycle %d: %s (expected 1111)' + % (self.tarcount, lad_bits)]]) if (self.tarcount != 1): self.tarcount += 1 @@ -301,9 +314,10 @@ class Decoder(srd.Decoder): self.tarcount = 0 self.state = 'IDLE' - # TODO: At which edge of the clock is data latched? Falling? - def decode(self, ss, es, data): - for (samplenum, pins) in data: + def decode(self): + while True: + # TODO: Come up with more appropriate self.wait() conditions. + pins = self.wait() # If none of the pins changed, there's nothing to do. if self.oldpins == pins: @@ -313,21 +327,21 @@ class Decoder(srd.Decoder): self.oldpins = pins # Get individual pin values into local variables. - # TODO: Handle optional pins. - (lframe, lreset, lclk, lad0, lad1, lad2, lad3) = pins + (lframe, lclk, lad0, lad1, lad2, lad3) = pins[:6] + (lreset, ldrq, serirq, clkrun, lpme, lpcpd, lsmi) = pins[6:] - # Only look at the signals upon falling LCLK edges. - # TODO: Rising? - ## if not (self.oldlclk == 1 and lclk == 0): - ## self.oldlclk = lclk - ## continue + # Only look at the signals upon rising LCLK edges. The LPC clock + # is the same as the PCI clock (which is sampled at rising edges). + if not (self.oldlclk == 0 and lclk == 1): + self.oldlclk = lclk + continue # Store LAD[3:0] bit values (one nibble) in local variables. # Most (but not all) states need this. if self.state != 'IDLE': lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0 - lad_bits = bin(lad)[2:].zfill(4) - # self.put(0, 0, self.out_ann, [0, ['LAD: %s' % lad_bits]]) + lad_bits = '{:04b}'.format(lad) + # self.putb([0, ['LAD: %s' % lad_bits]]) # TODO: Only memory read/write is currently supported/tested. @@ -335,10 +349,10 @@ class Decoder(srd.Decoder): if self.state == 'IDLE': # A valid LPC cycle starts with LFRAME# being asserted (low). if lframe != 0: - continue + continue + self.ss_block = self.samplenum self.state = 'GET START' self.lad = -1 - # self.clocknum = 0 elif self.state == 'GET START': self.handle_get_start(lad, lad_bits, lframe) elif self.state == 'GET CT/DR': @@ -353,6 +367,3 @@ class Decoder(srd.Decoder): self.handle_get_data(lad, lad_bits) elif self.state == 'GET TAR2': self.handle_get_tar2(lad, lad_bits) - else: - raise Exception('Invalid state: %s' % self.state) -