X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fjtag_stm32%2Fpd.py;h=9113b4cc16cc4e49443ccbffc6feac81e055bd79;hp=e30788c7dfc348b696213a25a2bc49014eb3798b;hb=e28f7aee3b96afeb543e0c3c29e3950ddd61a490;hpb=24c74fd30fb161837c5f8b01baf3c0fe2dfa4ed5

diff --git a/decoders/jtag_stm32/pd.py b/decoders/jtag_stm32/pd.py
index e30788c..9113b4c 100644
--- a/decoders/jtag_stm32/pd.py
+++ b/decoders/jtag_stm32/pd.py
@@ -1,5 +1,5 @@
 ##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
 ##
 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
 ##
@@ -18,8 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# ST STM32 JTAG protocol decoder
-
 import sigrokdecode as srd
 
 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
@@ -121,7 +119,7 @@ def data_out(bits):
            % (data_hex, ack_meaning)
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'jtag_stm32'
     name = 'JTAG / STM32'
     longname = 'Joint Test Action Group / ST STM32'
@@ -129,23 +127,16 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['jtag']
     outputs = ['jtag_stm32']
-    probes = []
-    optional_probes = []
-    options = {}
-    annotations = [
-        ['Text', 'Human-readable text'],
-    ]
+    annotations = (
+        ('text', 'Human-readable text'),
+    )
 
     def __init__(self, **kwargs):
         self.state = 'IDLE'
         # self.state = 'BYPASS'
 
-    def start(self, metadata):
-        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
-
-    def report(self):
-        pass
+    def start(self):
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def handle_reg_bypass(self, cmd, bits):
         # TODO
@@ -227,6 +218,4 @@ class Decoder(srd.Decoder):
             handle_reg(cmd, val)
             if cmd == 'DR TDO': # TODO: Assumes 'DR TDI' comes before 'DR TDO'
                 self.state = 'IDLE'
-        else:
-            raise Exception('Invalid state: %s' % self.state)