X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fjtag_ejtag%2Fpd.py;h=e2bf0a59ca73e52f8e6a414516813303aeb68e25;hp=38933ec56ca3e166963ce807e3a3e0d015056d33;hb=e144452bcdd5f2abbe6b6f3da41ad64f67e39def;hpb=aaaf37e1229ca414d4e077b3ce9d05cfd7b19e7f diff --git a/decoders/jtag_ejtag/pd.py b/decoders/jtag_ejtag/pd.py index 38933ec..e2bf0a5 100644 --- a/decoders/jtag_ejtag/pd.py +++ b/decoders/jtag_ejtag/pd.py @@ -18,6 +18,7 @@ ## import sigrokdecode as srd +from common.srdhelper import bin2int class Instruction(object): IDCODE = 0x01 @@ -158,9 +159,6 @@ ejtag_state_map = { Instruction.FASTDATA: State.FASTDATA, } -def bin_to_int(s: str): - return int('0b' + s, 2) - class RegData(object): def __init__(self): self.ss = None @@ -193,12 +191,13 @@ regs_items = { class Decoder(srd.Decoder): api_version = 3 id = 'jtag_ejtag' - name = 'JTAG / EJTAG (MIPS)' + name = 'JTAG / EJTAG' longname = 'Joint Test Action Group / EJTAG (MIPS)' desc = 'MIPS EJTAG protocol.' license = 'gplv2+' inputs = ['jtag'] - outputs = ['jtag_ejtag'] + outputs = [] + tags = ['Debug/trace'] annotations = ( ('instruction', 'Instruction'), ) + regs_items['ann'] + ( @@ -208,10 +207,10 @@ class Decoder(srd.Decoder): ) annotation_rows = ( ('instructions', 'Instructions', (0,)), - ('regs', 'Registers', regs_items['rows_range']), ('control_fields_in', 'Control fields in', (10,)), ('control_fields_out', 'Control fields out', (11,)), - ('pracc', 'PrAcc', (12,)), + ('regs', 'Registers', regs_items['rows_range']), + ('pracc-vals', 'PrAcc', (12,)), ) def __init__(self): @@ -225,7 +224,7 @@ class Decoder(srd.Decoder): self.put(self.ss, self.es, self.out_ann, data) def put_at(self, ss: int, es: int, data): - self.put(ss, es, self.out_ann, data); + self.put(ss, es, self.out_ann, data) def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -234,8 +233,8 @@ class Decoder(srd.Decoder): self.state = ejtag_state_map.get(ir_value, State.RESET) def parse_pracc(self): - control_in = bin_to_int(self.last_data['in']['data'][0]) - control_out = bin_to_int(self.last_data['out']['data'][0]) + control_in = bin2int(self.last_data['in']['data'][0]) + control_out = bin2int(self.last_data['out']['data'][0]) # Check if JTAG master acknowledges a pending PrAcc. if not ((not (control_in & ControlReg.PRACC)) and \ @@ -245,24 +244,23 @@ class Decoder(srd.Decoder): ss, es = self.pracc_state.ss, self.pracc_state.es pracc_write = (control_out & ControlReg.PRNW) != 0 - display_string = 'PrAcc: ' - display_string += 'Store' if pracc_write else 'Load/Fetch' + s = 'PrAcc: ' + s += 'Store' if pracc_write else 'Load/Fetch' if pracc_write: - if self.pracc_state.address_out != None: - display_string += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out) - if self.pracc_state.data_out != None: - display_string += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out) + if self.pracc_state.address_out is not None: + s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out) + if self.pracc_state.data_out is not None: + s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out) else: - if self.pracc_state.address_out != None: - display_string += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out) - if self.pracc_state.data_in != None: - display_string += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in) + if self.pracc_state.address_out is not None: + s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out) + if self.pracc_state.data_in is not None: + s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in) self.pracc_state.reset() - display_data = [Ann.PRACC, [display_string]] - self.put_at(ss, es, display_data) + self.put_at(ss, es, [Ann.PRACC, [s]]) def parse_control_reg(self, ann): reg_write = ann == Ann.CONTROL_FIELD_IN @@ -290,13 +288,12 @@ class Decoder(srd.Decoder): es = control_bit_positions[end_bit][1] value_str = control_data[end_bit : start_bit + 1] - value_index = bin_to_int(value_str) + value_index = bin2int(value_str) short_desc = comment + ': ' + value_str long_desc = value_descriptions[value_index] if len(value_descriptions) > value_index else '?' - display_data = [ann, [short_desc, long_desc]] - self.put_at(ss, es, display_data) + self.put_at(ss, es, [ann, [long_desc, short_desc]]) def check_last_data(self): if not hasattr(self, 'last_data'): @@ -315,7 +312,7 @@ class Decoder(srd.Decoder): bitstring = val[0] bit_sample_pos = val[1] fastdata_state = bitstring[32] - data = bin_to_int(bitstring[0:32]) + data = bin2int(bitstring[0:32]) fastdata_bit_pos = bit_sample_pos[32] data_pos = [bit_sample_pos[31][0], bit_sample_pos[0][1]] @@ -335,7 +332,7 @@ class Decoder(srd.Decoder): self.put_at(ss_data, es_data, display_data) def handle_dr_tdi(self, val): - value = bin_to_int(val[0]) + value = bin2int(val[0]) self.check_last_data() self.last_data['in'] = {'ss': self.ss, 'es': self.es, 'data': val} @@ -349,7 +346,7 @@ class Decoder(srd.Decoder): self.handle_fastdata(val, Ann.CONTROL_FIELD_IN) def handle_dr_tdo(self, val): - value = bin_to_int(val[0]) + value = bin2int(val[0]) self.check_last_data() self.last_data['out'] = {'ss': self.ss, 'es': self.es, 'data': val} if self.state == State.ADDRESS: @@ -360,17 +357,17 @@ class Decoder(srd.Decoder): self.handle_fastdata(val, Ann.CONTROL_FIELD_OUT) def handle_ir_tdi(self, val): - code = bin_to_int(val[0]) - hex = '0x{:02X}'.format(code) + code = bin2int(val[0]) + hexval = '0x{:02X}'.format(code) if code in ejtag_insn: # Format instruction name. insn = ejtag_insn[code] s_short = insn[0] - s_long = insn[0] + ': ' + insn[1] + ' (' + hex + ')' + s_long = insn[0] + ': ' + insn[1] + ' (' + hexval + ')' # Display it and select data register. - self.put_current([Ann.INSTRUCTION, [s_short, s_long]]) + self.put_current([Ann.INSTRUCTION, [s_long, s_short]]) else: - self.put_current([Ann.INSTRUCTION, [hex, 'IR TDI ({})'.format(hex)]]) + self.put_current([Ann.INSTRUCTION, [hexval, 'IR TDI ({})'.format(hexval)]]) self.select_reg(code) def handle_new_state(self, new_state):