X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fjtag_ejtag%2Fpd.py;h=ceaa1142dd6f02bda715b30823bbe800a5b5564e;hp=9af3ad7fce4eb29cfa3db203edc6f5f245fed3b4;hb=f78b814d54b19233d5e3f7cfef3d30a7a5ac8d40;hpb=d1b7bd1b602149cef4183f5a05188c0467bcd280 diff --git a/decoders/jtag_ejtag/pd.py b/decoders/jtag_ejtag/pd.py index 9af3ad7..ceaa114 100644 --- a/decoders/jtag_ejtag/pd.py +++ b/decoders/jtag_ejtag/pd.py @@ -18,6 +18,7 @@ ## import sigrokdecode as srd +from common.srdhelper import bin2int class Instruction(object): IDCODE = 0x01 @@ -158,9 +159,6 @@ ejtag_state_map = { Instruction.FASTDATA: State.FASTDATA, } -def bin_to_int(s: str): - return int('0b' + s, 2) - class RegData(object): def __init__(self): self.ss = None @@ -225,20 +223,17 @@ class Decoder(srd.Decoder): self.put(self.ss, self.es, self.out_ann, data) def put_at(self, ss: int, es: int, data): - self.put(ss, es, self.out_ann, data); + self.put(ss, es, self.out_ann, data) def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) def select_reg(self, ir_value: int): - if ir_value in ejtag_state_map: - self.state = ejtag_state_map[ir_value] - else: - self.state = State.RESET + self.state = ejtag_state_map.get(ir_value, State.RESET) def parse_pracc(self): - control_in = bin_to_int(self.last_data['in']['data'][0]) - control_out = bin_to_int(self.last_data['out']['data'][0]) + control_in = bin2int(self.last_data['in']['data'][0]) + control_out = bin2int(self.last_data['out']['data'][0]) # Check if JTAG master acknowledges a pending PrAcc. if not ((not (control_in & ControlReg.PRACC)) and \ @@ -248,34 +243,28 @@ class Decoder(srd.Decoder): ss, es = self.pracc_state.ss, self.pracc_state.es pracc_write = (control_out & ControlReg.PRNW) != 0 - display_string = 'PrAcc: ' - display_string += 'Store' if pracc_write else 'Load/Fetch' + s = 'PrAcc: ' + s += 'Store' if pracc_write else 'Load/Fetch' if pracc_write: - if self.pracc_state.address_out != None: - display_string += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out) - if self.pracc_state.data_out != None: - display_string += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out) + if self.pracc_state.address_out is not None: + s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out) + if self.pracc_state.data_out is not None: + s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out) else: - if self.pracc_state.address_out != None: - display_string += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out) - if self.pracc_state.data_in != None: - display_string += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in) + if self.pracc_state.address_out is not None: + s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out) + if self.pracc_state.data_in is not None: + s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in) self.pracc_state.reset() - display_data = [Ann.PRACC, [display_string]] - self.put_at(ss, es, display_data) + self.put_at(ss, es, [Ann.PRACC, [s]]) def parse_control_reg(self, ann): reg_write = ann == Ann.CONTROL_FIELD_IN control_bit_positions = [] - data_select = '' - - if reg_write: - data_select = 'in' - else: - data_select = 'out' + data_select = 'in' if (reg_write) else 'out' control_bit_positions = self.last_data[data_select]['data'][1] control_data = self.last_data[data_select]['data'][0] @@ -298,13 +287,12 @@ class Decoder(srd.Decoder): es = control_bit_positions[end_bit][1] value_str = control_data[end_bit : start_bit + 1] - value_index = bin_to_int(value_str) + value_index = bin2int(value_str) short_desc = comment + ': ' + value_str long_desc = value_descriptions[value_index] if len(value_descriptions) > value_index else '?' - display_data = [ann, [short_desc, long_desc]] - self.put_at(ss, es, display_data) + self.put_at(ss, es, [ann, [long_desc, short_desc]]) def check_last_data(self): if not hasattr(self, 'last_data'): @@ -323,7 +311,7 @@ class Decoder(srd.Decoder): bitstring = val[0] bit_sample_pos = val[1] fastdata_state = bitstring[32] - data = bin_to_int(bitstring[0:32]) + data = bin2int(bitstring[0:32]) fastdata_bit_pos = bit_sample_pos[32] data_pos = [bit_sample_pos[31][0], bit_sample_pos[0][1]] @@ -343,7 +331,7 @@ class Decoder(srd.Decoder): self.put_at(ss_data, es_data, display_data) def handle_dr_tdi(self, val): - value = bin_to_int(val[0]) + value = bin2int(val[0]) self.check_last_data() self.last_data['in'] = {'ss': self.ss, 'es': self.es, 'data': val} @@ -357,7 +345,7 @@ class Decoder(srd.Decoder): self.handle_fastdata(val, Ann.CONTROL_FIELD_IN) def handle_dr_tdo(self, val): - value = bin_to_int(val[0]) + value = bin2int(val[0]) self.check_last_data() self.last_data['out'] = {'ss': self.ss, 'es': self.es, 'data': val} if self.state == State.ADDRESS: @@ -368,7 +356,7 @@ class Decoder(srd.Decoder): self.handle_fastdata(val, Ann.CONTROL_FIELD_OUT) def handle_ir_tdi(self, val): - code = bin_to_int(val[0]) + code = bin2int(val[0]) hex = '0x{:02X}'.format(code) if code in ejtag_insn: # Format instruction name. @@ -376,7 +364,7 @@ class Decoder(srd.Decoder): s_short = insn[0] s_long = insn[0] + ': ' + insn[1] + ' (' + hex + ')' # Display it and select data register. - self.put_current([Ann.INSTRUCTION, [s_short, s_long]]) + self.put_current([Ann.INSTRUCTION, [s_long, s_short]]) else: self.put_current([Ann.INSTRUCTION, [hex, 'IR TDI ({})'.format(hex)]]) self.select_reg(code)