X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fjtag%2Fpd.py;h=b44ab527421d1e3f2dfdc5912755929d5190685a;hp=0bb4069d66cabc8fe27c8b093f8bfd382cf49db2;hb=f7332ee0869cea37577257126acfe40bbe9f4db4;hpb=780770f1295b7fdeb4481eb42623bad5da1e19a7 diff --git a/decoders/jtag/pd.py b/decoders/jtag/pd.py index 0bb4069..b44ab52 100644 --- a/decoders/jtag/pd.py +++ b/decoders/jtag/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2012-2013 Uwe Hermann +## Copyright (C) 2012-2015 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -23,21 +23,25 @@ import sigrokdecode as srd ''' OUTPUT_PYTHON format: -JTAG packet: -[, ] +Packet: +[, ] - is one of: - - 'NEW STATE': is the new state of the JTAG state machine. +: + - 'NEW STATE': is the new state of the JTAG state machine. Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN', 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR', 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR', 'EXIT2-IR', 'UPDATE-IR'. + - 'IR TDI BIT': Bit that was clocked into the IR register. + - 'IR TDO BIT': Bit that was clocked out of the IR register. + - 'DR TDI BIT': Bit that was clocked into the DR register. + - 'DR TDO BIT': Bit that was clocked out of the DR register. - 'IR TDI': Bitstring that was clocked into the IR register. - 'IR TDO': Bitstring that was clocked out of the IR register. - 'DR TDI': Bitstring that was clocked into the DR register. - 'DR TDO': Bitstring that was clocked out of the DR register. - - ... +All bits are either '1' or '0' characters. All bitstrings are a sequence of '1' and '0' characters. The right-most character in the bitstring is the LSB. Example: '01110001' (1 is LSB). ''' @@ -54,7 +58,7 @@ jtag_states = [ ] class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'jtag' name = 'JTAG' longname = 'Joint Test Action Group (IEEE 1149.1)' @@ -62,18 +66,18 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['jtag'] - probes = [ + channels = ( {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'}, {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'}, {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'}, {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'}, - ] - optional_probes = [ + ) + optional_channels = ( {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'}, {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'}, {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'}, - ] - annotations = [[s.lower(), s] for s in jtag_states] + ) + annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) def __init__(self, **kwargs): # self.state = 'TEST-LOGIC-RESET' @@ -139,14 +143,11 @@ class Decoder(srd.Decoder): elif self.state == 'UPDATE-IR': self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' - else: - raise Exception('Invalid state: %s' % self.state) - def handle_rising_tck_edge(self, tdi, tdo, tck, tms): # Rising TCK edges always advance the state machine. self.advance_state_machine(tms) - if self.first == True: + if self.first: # Save the start sample and item for later (no output yet). self.ss_item = self.samplenum self.first = False @@ -165,9 +166,10 @@ class Decoder(srd.Decoder): if self.state.startswith('SHIFT-') and self.oldstate == self.state: self.bits_tdi.insert(0, tdi) self.bits_tdo.insert(0, tdo) - # TODO: ANN/PROTO output. - # self.putx([0, ['TDI add: ' + str(tdi)]]) - # self.putp([0, ['TDO add: ' + str(tdo)]]) + self.putx([0, [self.state[-2:] + ' TDI BIT: ' + str(tdi)]]) + self.putx([0, [self.state[-2:] + ' TDO BIT: ' + str(tdo)]]) + self.putp([self.state[-2:] + ' TDI BIT', str(tdi)]) + self.putp([self.state[-2:] + ' TDO BIT', str(tdo)]) # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*. if self.oldstate.startswith('SHIFT-') and \ @@ -177,16 +179,16 @@ class Decoder(srd.Decoder): b = ''.join(map(str, self.bits_tdi)) h = ' (0x%x' % int('0b' + b, 2) + ')' s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits' - # self.putx([0, [s]]) - # self.putp([t, b]) + self.putx([0, [s]]) + self.putp([t, b]) self.bits_tdi = [] t = self.state[-2:] + ' TDO' b = ''.join(map(str, self.bits_tdo)) h = ' (0x%x' % int('0b' + b, 2) + ')' s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits' - # self.putx([0, [s]]) - # self.putp([t, b]) + self.putx([0, [s]]) + self.putp([t, b]) self.bits_tdo = [] def decode(self, ss, es, data): @@ -200,7 +202,7 @@ class Decoder(srd.Decoder): self.oldpins = pins # Get individual pin values into local variables. - # Unused probes will have a value of > 1. + # Unused channels will have a value of > 1. (tdi, tdo, tck, tms, trst, srst, rtck) = pins # We only care about TCK edges (either rising or falling). @@ -210,11 +212,7 @@ class Decoder(srd.Decoder): # Store start/end sample for later usage. self.ss, self.es = ss, es - # self.putx([0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \ - # % (tdi, tdo, tck, tms)]]) - if (self.oldtck == 0 and tck == 1): self.handle_rising_tck_edge(tdi, tdo, tck, tms) self.oldtck = tck -