X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fjtag%2Fpd.py;h=0bb4069d66cabc8fe27c8b093f8bfd382cf49db2;hp=b4fa4200d163985ec7e9a954a49c877d9dd09122;hb=780770f1295b7fdeb4481eb42623bad5da1e19a7;hpb=50bd5d259677faf87bb3408e111d0e833d7ba9b4 diff --git a/decoders/jtag/pd.py b/decoders/jtag/pd.py index b4fa420..0bb4069 100644 --- a/decoders/jtag/pd.py +++ b/decoders/jtag/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2012 Uwe Hermann +## Copyright (C) 2012-2013 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,10 +18,41 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# JTAG protocol decoder - import sigrokdecode as srd +''' +OUTPUT_PYTHON format: + +JTAG packet: +[, ] + + is one of: + - 'NEW STATE': is the new state of the JTAG state machine. + Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN', + 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR', + 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR', + 'EXIT2-IR', 'UPDATE-IR'. + - 'IR TDI': Bitstring that was clocked into the IR register. + - 'IR TDO': Bitstring that was clocked out of the IR register. + - 'DR TDI': Bitstring that was clocked into the DR register. + - 'DR TDO': Bitstring that was clocked out of the DR register. + - ... + +All bitstrings are a sequence of '1' and '0' characters. The right-most +character in the bitstring is the LSB. Example: '01110001' (1 is LSB). +''' + +jtag_states = [ + # Intro "tree" + 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', + # DR "tree" + 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR', + 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR', + # IR "tree" + 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR', + 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR', +] + class Decoder(srd.Decoder): api_version = 1 id = 'jtag' @@ -42,10 +73,7 @@ class Decoder(srd.Decoder): {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'}, {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'}, ] - options = {} - annotations = [ - ['Text', 'Human-readable text'], - ] + annotations = [[s.lower(), s] for s in jtag_states] def __init__(self, **kwargs): # self.state = 'TEST-LOGIC-RESET' @@ -55,13 +83,20 @@ class Decoder(srd.Decoder): self.oldtck = -1 self.bits_tdi = [] self.bits_tdo = [] + self.samplenum = 0 + self.ss_item = self.es_item = None + self.saved_item = None + self.first = True - def start(self, metadata): - self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag') - self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag') + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) - def report(self): - pass + def putx(self, data): + self.put(self.ss_item, self.es_item, self.out_ann, data) + + def putp(self, data): + self.put(self.ss_item, self.es_item, self.out_python, data) def advance_state_machine(self, tms): self.oldstate = self.state @@ -111,11 +146,19 @@ class Decoder(srd.Decoder): # Rising TCK edges always advance the state machine. self.advance_state_machine(tms) - # Output the state we just switched to. - self.put(self.ss, self.es, self.out_ann, - [0, ['New state: %s' % self.state]]) - self.put(self.ss, self.es, self.out_proto, - ['NEW STATE', self.state]) + if self.first == True: + # Save the start sample and item for later (no output yet). + self.ss_item = self.samplenum + self.first = False + self.saved_item = self.state + else: + # Output the saved item (from the last CLK edge to the current). + self.es_item = self.samplenum + # Output the state we just switched to. + self.putx([jtag_states.index(self.state), [self.state]]) + self.putp(['NEW STATE', self.state]) + self.ss_item = self.samplenum + self.saved_item = self.state # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR, # collect the current TDI/TDO values (upon rising TCK edge). @@ -123,10 +166,8 @@ class Decoder(srd.Decoder): self.bits_tdi.insert(0, tdi) self.bits_tdo.insert(0, tdo) # TODO: ANN/PROTO output. - # self.put(self.ss, self.es, self.out_ann, - # [0, ['TDI add: ' + str(tdi)]]) - # self.put(self.ss, self.es, self.out_ann, - # [0, ['TDO add: ' + str(tdo)]]) + # self.putx([0, ['TDI add: ' + str(tdi)]]) + # self.putp([0, ['TDO add: ' + str(tdo)]]) # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*. if self.oldstate.startswith('SHIFT-') and \ @@ -136,20 +177,20 @@ class Decoder(srd.Decoder): b = ''.join(map(str, self.bits_tdi)) h = ' (0x%x' % int('0b' + b, 2) + ')' s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits' - self.put(self.ss, self.es, self.out_ann, [0, [s]]) - self.put(self.ss, self.es, self.out_proto, [t, b]) + # self.putx([0, [s]]) + # self.putp([t, b]) self.bits_tdi = [] t = self.state[-2:] + ' TDO' b = ''.join(map(str, self.bits_tdo)) h = ' (0x%x' % int('0b' + b, 2) + ')' s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits' - self.put(self.ss, self.es, self.out_ann, [0, [s]]) - self.put(self.ss, self.es, self.out_proto, [t, b]) + # self.putx([0, [s]]) + # self.putp([t, b]) self.bits_tdo = [] def decode(self, ss, es, data): - for (samplenum, pins) in data: + for (self.samplenum, pins) in data: # If none of the pins changed, there's nothing to do. if self.oldpins == pins: @@ -169,9 +210,8 @@ class Decoder(srd.Decoder): # Store start/end sample for later usage. self.ss, self.es = ss, es - # self.put(self.ss, self.es, self.out_ann, - # [0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \ - # % (tdi, tdo, tck, tms)]]) + # self.putx([0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \ + # % (tdi, tdo, tck, tms)]]) if (self.oldtck == 0 and tck == 1): self.handle_rising_tck_edge(tdi, tdo, tck, tms)