X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fjtag%2Fpd.py;h=00602bb1a07e2452417d4154d73572e3fab1e212;hp=25f26342183ba14bebc181fbeffeb85d4616ee58;hb=HEAD;hpb=bf69977d12886794ac597083403859ac99ab38ac diff --git a/decoders/jtag/pd.py b/decoders/jtag/pd.py index 25f2634..5fa63ab 100644 --- a/decoders/jtag/pd.py +++ b/decoders/jtag/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2012-2013 Uwe Hermann +## Copyright (C) 2012-2020 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,11 +14,11 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd +from common.srdhelper import SrdStrEnum ''' OUTPUT_PYTHON format: @@ -36,25 +36,22 @@ Packet: - 'IR TDO': Bitstring that was clocked out of the IR register. - 'DR TDI': Bitstring that was clocked into the DR register. - 'DR TDO': Bitstring that was clocked out of the DR register. - - ... -All bitstrings are a sequence of '1' and '0' characters. The right-most -character in the bitstring is the LSB. Example: '01110001' (1 is LSB). +All bitstrings are a list consisting of two items. The first is a sequence +of '1' and '0' characters (the right-most character is the LSB. Example: +'01110001', where 1 is the LSB). The second item is a list of ss/es values +for each bit that is in the bitstring. ''' -jtag_states = [ - # Intro "tree" - 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', - # DR "tree" - 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR', - 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR', - # IR "tree" - 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR', - 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR', -] +s = 'TEST-LOGIC-RESET RUN-TEST/IDLE \ + SELECT-DR-SCAN CAPTURE-DR UPDATE-DR PAUSE-DR SHIFT-DR EXIT1-DR EXIT2-DR \ + SELECT-IR-SCAN CAPTURE-IR UPDATE-IR PAUSE-IR SHIFT-IR EXIT1-IR EXIT2-IR' +St = SrdStrEnum.from_str('St', s) + +jtag_states = [s.value for s in St] class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'jtag' name = 'JTAG' longname = 'Joint Test Action Group (IEEE 1149.1)' @@ -62,6 +59,7 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['jtag'] + tags = ['Debug/trace'] channels = ( {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'}, {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'}, @@ -73,20 +71,36 @@ class Decoder(srd.Decoder): {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'}, {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'}, ) - annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \ + ('bit-tdi', 'Bit (TDI)'), + ('bit-tdo', 'Bit (TDO)'), + ('bitstring-tdi', 'Bitstring (TDI)'), + ('bitstring-tdo', 'Bitstring (TDO)'), + ) + annotation_rows = ( + ('bits-tdi', 'Bits (TDI)', (16,)), + ('bits-tdo', 'Bits (TDO)', (17,)), + ('bitstrings-tdi', 'Bitstrings (TDI)', (18,)), + ('bitstrings-tdo', 'Bitstrings (TDO)', (19,)), + ('states', 'States', tuple(range(15 + 1))), + ) + + def __init__(self): + self.reset() - def __init__(self, **kwargs): - # self.state = 'TEST-LOGIC-RESET' - self.state = 'RUN-TEST/IDLE' + def reset(self): + # self.state = St.TEST_LOGIC_RESET + self.state = St.RUN_TEST_IDLE self.oldstate = None - self.oldpins = (-1, -1, -1, -1) - self.oldtck = -1 self.bits_tdi = [] self.bits_tdo = [] - self.samplenum = 0 + self.bits_samplenums_tdi = [] + self.bits_samplenums_tdo = [] self.ss_item = self.es_item = None + self.ss_bitstring = self.es_bitstring = None self.saved_item = None self.first = True + self.first_bit = True def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -98,123 +112,124 @@ class Decoder(srd.Decoder): def putp(self, data): self.put(self.ss_item, self.es_item, self.out_python, data) + def putx_bs(self, data): + self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data) + + def putp_bs(self, data): + self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data) + def advance_state_machine(self, tms): self.oldstate = self.state # Intro "tree" - if self.state == 'TEST-LOGIC-RESET': - self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE' - elif self.state == 'RUN-TEST/IDLE': - self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' + if self.state == St.TEST_LOGIC_RESET: + self.state = St.TEST_LOGIC_RESET if (tms) else St.RUN_TEST_IDLE + elif self.state == St.RUN_TEST_IDLE: + self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE # DR "tree" - elif self.state == 'SELECT-DR-SCAN': - self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR' - elif self.state == 'CAPTURE-DR': - self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR' - elif self.state == 'SHIFT-DR': - self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR' - elif self.state == 'EXIT1-DR': - self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR' - elif self.state == 'PAUSE-DR': - self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR' - elif self.state == 'EXIT2-DR': - self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR' - elif self.state == 'UPDATE-DR': - self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' + elif self.state == St.SELECT_DR_SCAN: + self.state = St.SELECT_IR_SCAN if (tms) else St.CAPTURE_DR + elif self.state == St.CAPTURE_DR: + self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR + elif self.state == St.SHIFT_DR: + self.state = St.EXIT1_DR if (tms) else St.SHIFT_DR + elif self.state == St.EXIT1_DR: + self.state = St.UPDATE_DR if (tms) else St.PAUSE_DR + elif self.state == St.PAUSE_DR: + self.state = St.EXIT2_DR if (tms) else St.PAUSE_DR + elif self.state == St.EXIT2_DR: + self.state = St.UPDATE_DR if (tms) else St.SHIFT_DR + elif self.state == St.UPDATE_DR: + self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE # IR "tree" - elif self.state == 'SELECT-IR-SCAN': - self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR' - elif self.state == 'CAPTURE-IR': - self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR' - elif self.state == 'SHIFT-IR': - self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR' - elif self.state == 'EXIT1-IR': - self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR' - elif self.state == 'PAUSE-IR': - self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR' - elif self.state == 'EXIT2-IR': - self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR' - elif self.state == 'UPDATE-IR': - self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE' + elif self.state == St.SELECT_IR_SCAN: + self.state = St.TEST_LOGIC_RESET if (tms) else St.CAPTURE_IR + elif self.state == St.CAPTURE_IR: + self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR + elif self.state == St.SHIFT_IR: + self.state = St.EXIT1_IR if (tms) else St.SHIFT_IR + elif self.state == St.EXIT1_IR: + self.state = St.UPDATE_IR if (tms) else St.PAUSE_IR + elif self.state == St.PAUSE_IR: + self.state = St.EXIT2_IR if (tms) else St.PAUSE_IR + elif self.state == St.EXIT2_IR: + self.state = St.UPDATE_IR if (tms) else St.SHIFT_IR + elif self.state == St.UPDATE_IR: + self.state = St.SELECT_DR_SCAN if (tms) else St.RUN_TEST_IDLE + + def handle_rising_tck_edge(self, pins): + (tdi, tdo, tck, tms, trst, srst, rtck) = pins - else: - raise Exception('Invalid state: %s' % self.state) - - def handle_rising_tck_edge(self, tdi, tdo, tck, tms): # Rising TCK edges always advance the state machine. self.advance_state_machine(tms) - if self.first == True: + if self.first: # Save the start sample and item for later (no output yet). self.ss_item = self.samplenum self.first = False - self.saved_item = self.state else: # Output the saved item (from the last CLK edge to the current). self.es_item = self.samplenum - # Output the state we just switched to. - self.putx([jtag_states.index(self.state), [self.state]]) - self.putp(['NEW STATE', self.state]) - self.ss_item = self.samplenum - self.saved_item = self.state - - # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR, - # collect the current TDI/TDO values (upon rising TCK edge). - if self.state.startswith('SHIFT-') and self.oldstate == self.state: - self.bits_tdi.insert(0, tdi) - self.bits_tdo.insert(0, tdo) - # TODO: ANN/PROTO output. - # self.putx([0, ['TDI add: ' + str(tdi)]]) - # self.putp([0, ['TDO add: ' + str(tdo)]]) - - # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*. - if self.oldstate.startswith('SHIFT-') and \ - self.state.startswith('EXIT1-'): - - t = self.state[-2:] + ' TDI' - b = ''.join(map(str, self.bits_tdi)) - h = ' (0x%x' % int('0b' + b, 2) + ')' - s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits' - # self.putx([0, [s]]) - # self.putp([t, b]) + # Output the old state (from last rising TCK edge to current one). + self.putx([jtag_states.index(self.oldstate.value), [self.oldstate.value]]) + self.putp(['NEW STATE', self.state.value]) + + # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values. + if self.oldstate.value.startswith('SHIFT-') or \ + self.oldstate.value.startswith('EXIT1-'): + if self.first_bit: + self.ss_bitstring = self.samplenum + self.first_bit = False + else: + self.putx([16, [str(self.bits_tdi[-1])]]) + self.putx([17, [str(self.bits_tdo[-1])]]) + # Use self.samplenum as ES of the previous bit. + self.bits_samplenums_tdi[-1][1] = self.samplenum + self.bits_samplenums_tdo[-1][1] = self.samplenum + + self.bits_tdi.append(tdi) + self.bits_tdo.append(tdo) + + # Use self.samplenum as SS of the current bit. + self.bits_samplenums_tdi.append([self.samplenum, -1]) + self.bits_samplenums_tdo.append([self.samplenum, -1]) + + # Output all TDI/TDO bits if we just switched to UPDATE-*. + if self.state.value.startswith('UPDATE-'): + + self.es_bitstring = self.samplenum + + t = self.state.value[-2:] + ' TDI' + self.bits_tdi.reverse() + self.bits_samplenums_tdi.reverse() + b = ''.join(map(str, self.bits_tdi[1:])) + h = ' (0x%x' % int('0b0' + b, 2) + ')' + s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits' + self.putx_bs([18, [s]]) + self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]]) self.bits_tdi = [] - - t = self.state[-2:] + ' TDO' - b = ''.join(map(str, self.bits_tdo)) - h = ' (0x%x' % int('0b' + b, 2) + ')' - s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits' - # self.putx([0, [s]]) - # self.putp([t, b]) + self.bits_samplenums_tdi = [] + + t = self.state.value[-2:] + ' TDO' + self.bits_tdo.reverse() + self.bits_samplenums_tdo.reverse() + b = ''.join(map(str, self.bits_tdo[1:])) + h = ' (0x%x' % int('0b0' + b, 2) + ')' + s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits' + self.putx_bs([19, [s]]) + self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]]) self.bits_tdo = [] + self.bits_samplenums_tdo = [] - def decode(self, ss, es, data): - for (self.samplenum, pins) in data: - - # If none of the pins changed, there's nothing to do. - if self.oldpins == pins: - continue - - # Store current pin values for the next round. - self.oldpins = pins - - # Get individual pin values into local variables. - # Unused channels will have a value of > 1. - (tdi, tdo, tck, tms, trst, srst, rtck) = pins - - # We only care about TCK edges (either rising or falling). - if (self.oldtck == tck): - continue - - # Store start/end sample for later usage. - self.ss, self.es = ss, es - - # self.putx([0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \ - # % (tdi, tdo, tck, tms)]]) + self.first_bit = True - if (self.oldtck == 0 and tck == 1): - self.handle_rising_tck_edge(tdi, tdo, tck, tms) + self.ss_bitstring = self.samplenum - self.oldtck = tck + self.ss_item = self.samplenum + def decode(self): + while True: + # Wait for a rising edge on TCK. + self.handle_rising_tck_edge(self.wait({2: 'r'}))