X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fjitter%2Fpd.py;h=5343fbf0fbc069145514b916b7deb2e1f9d32a91;hp=d40c643ed64303fe7cffdc32f5c9822181c6010a;hb=6cbba91f23b9f9ace75b4722c9c0776b9211008d;hpb=2824e81140d3a8e37464f758cf67f50f2f7afca7 diff --git a/decoders/jitter/pd.py b/decoders/jitter/pd.py index d40c643..5343fbf 100644 --- a/decoders/jitter/pd.py +++ b/decoders/jitter/pd.py @@ -14,8 +14,7 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd @@ -31,14 +30,15 @@ class SamplerateError(Exception): pass class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'jitter' name = 'Jitter' longname = 'Timing jitter calculation' desc = 'Retrieves the timing jitter between two digital signals.' license = 'gplv2+' inputs = ['logic'] - outputs = ['jitter'] + outputs = [] + tags = ['Clock/timing', 'Util'] channels = ( {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'}, {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'}, @@ -63,11 +63,13 @@ class Decoder(srd.Decoder): ('ascii-float', 'Jitter values as newline-separated ASCII floats'), ) - def __init__(self, **kwargs): + def __init__(self): + self.reset() + + def reset(self): self.state = 'CLK' self.samplerate = None - self.oldpin = None - self.oldclk = self.oldsig = None + self.oldclk, self.oldsig = 0, 0 self.clk_start = None self.sig_start = None self.clk_missed = 0 @@ -77,7 +79,7 @@ class Decoder(srd.Decoder): self.clk_edge = edge_detector[self.options['clk_polarity']] self.sig_edge = edge_detector[self.options['sig_polarity']] self.out_ann = self.register(srd.OUTPUT_ANN) - self.out_bin = self.register(srd.OUTPUT_BINARY) + self.out_binary = self.register(srd.OUTPUT_BINARY) self.out_clk_missed = self.register(srd.OUTPUT_META, meta=(int, 'Clock missed', 'Clock transition missed')) self.out_sig_missed = self.register(srd.OUTPUT_META, @@ -91,17 +93,17 @@ class Decoder(srd.Decoder): def putx(self, delta): # Adjust granularity. if delta == 0 or delta >= 1: - delta_s = "%.1fs" % (delta) + delta_s = '%.1fs' % (delta) elif delta <= 1e-12: - delta_s = "%.1ffs" % (delta * 1e15) + delta_s = '%.1ffs' % (delta * 1e15) elif delta <= 1e-9: - delta_s = "%.1fps" % (delta * 1e12) + delta_s = '%.1fps' % (delta * 1e12) elif delta <= 1e-6: - delta_s = "%.1fns" % (delta * 1e9) + delta_s = '%.1fns' % (delta * 1e9) elif delta <= 1e-3: - delta_s = "%.1fμs" % (delta * 1e6) + delta_s = '%.1fμs' % (delta * 1e6) else: - delta_s = "%.1fms" % (delta * 1e3) + delta_s = '%.1fms' % (delta * 1e3) self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]]) @@ -111,7 +113,7 @@ class Decoder(srd.Decoder): return # Format the delta to an ASCII float value terminated by a newline. x = str(delta) + '\n' - self.put(self.clk_start, self.sig_start, self.out_bin, + self.put(self.clk_start, self.sig_start, self.out_binary, [0, x.encode('UTF-8')]) # Helper function for missed clock and signal annotations. @@ -174,19 +176,12 @@ class Decoder(srd.Decoder): # everything we can with this sample. return True - def decode(self, ss, es, data): + def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') - - for (self.samplenum, pins) in data: - # We are only interested in transitions. - if self.oldpin == pins: - continue - - self.oldpin, (clk, sig) = pins, pins - - if self.oldclk is None and self.oldsig is None: - self.oldclk, self.oldsig = clk, sig + while True: + # Wait for a transition on CLK and/or SIG. + clk, sig = self.wait([{0: 'e'}, {1: 'e'}]) # State machine: # For each sample we can move 2 steps forward in the state machine.