X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fir_rc5%2Fpd.py;h=60a94160498a3beac0e74f31c1eec5b67c57d288;hp=25a4576e71b378b03290dc5c12bd6e4429719ddc;hb=719bde9b1c078bfc61b800f6bddf43c5e3d4e0d6;hpb=92d992d2e50a1996fa2f436f5217b5a9fb3b7e62 diff --git a/decoders/ir_rc5/pd.py b/decoders/ir_rc5/pd.py index 25a4576..60a9416 100644 --- a/decoders/ir_rc5/pd.py +++ b/decoders/ir_rc5/pd.py @@ -14,15 +14,17 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd from .lists import * +class SamplerateError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 3 id = 'ir_rc5' name = 'IR RC-5' longname = 'IR RC-5' @@ -30,32 +32,36 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['ir_rc5'] - probes = [ + channels = ( {'id': 'ir', 'name': 'IR', 'desc': 'IR data line'}, - ] - optional_probes = [] - options = { - 'polarity': ['Polarity', 'active-low'], - 'protocol': ['Protocol type', 'standard'], - } - annotations = [ - ['bit', 'Bit'], - ['startbit1', 'Startbit 1'], - ['startbit2', 'Startbit 2'], - ['togglebit-0', 'Toggle bit 0'], - ['togglebit-1', 'Toggle bit 1'], - ['address', 'Address'], - ['command', 'Command'], - ] + ) + options = ( + {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-low', + 'values': ('active-low', 'active-high')}, + {'id': 'protocol', 'desc': 'Protocol type', 'default': 'standard', + 'values': ('standard', 'extended')}, + ) + annotations = ( + ('bit', 'Bit'), + ('startbit1', 'Startbit 1'), + ('startbit2', 'Startbit 2'), + ('togglebit-0', 'Toggle bit 0'), + ('togglebit-1', 'Toggle bit 1'), + ('address', 'Address'), + ('command', 'Command'), + ) annotation_rows = ( ('bits', 'Bits', (0,)), ('fields', 'Fields', (1, 2, 3, 4, 5, 6)), ) - def __init__(self, **kwargs): + def __init__(self): + self.reset() + + def reset(self): self.samplerate = None self.samplenum = None - self.edges, self.bits, self.bits_ss_es = [], [], [] + self.edges, self.bits, self.ss_es_bits = [], [], [] self.state = 'IDLE' def start(self): @@ -69,7 +75,7 @@ class Decoder(srd.Decoder): self.halfbit = int((self.samplerate * 0.00178) / 2.0) def putb(self, bit1, bit2, data): - ss, es = self.bits_ss_es[bit1][0], self.bits_ss_es[bit2][1] + ss, es = self.ss_es_bits[bit1][0], self.ss_es_bits[bit2][1] self.put(ss, es, self.out_ann, data) def handle_bits(self): @@ -79,9 +85,9 @@ class Decoder(srd.Decoder): if i == 0: ss = max(0, self.bits[0][0] - self.halfbit) else: - ss = self.bits_ss_es[i - 1][1] + ss = self.ss_es_bits[i - 1][1] es = self.bits[i][0] + self.halfbit - self.bits_ss_es.append([ss, es]) + self.ss_es_bits.append([ss, es]) self.putb(i, i, [0, ['%d' % self.bits[i][1]]]) # Bits[0:0]: Startbit 1 s = ['Startbit1: %d' % b[0][1], 'SB1: %d' % b[0][1], 'SB1', 'S1', 'S'] @@ -125,14 +131,18 @@ class Decoder(srd.Decoder): elif distance in range(s - margin, s + margin + 1): return 's' else: - raise Exception('Invalid edge distance: %d' % distance) + return 'e' # Error, invalid edge distance. - def decode(self, ss, es, data): - if self.samplerate is None: - raise Exception("Cannot decode without samplerate.") - for (self.samplenum, pins) in data: + def reset_decoder_state(self): + self.edges, self.bits, self.ss_es_bits = [], [], [] + self.state = 'IDLE' - self.ir = pins[0] + def decode(self): + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') + while True: + + (self.ir,) = self.wait() # Wait for any edge (rising or falling). if self.old_ir == self.ir: @@ -140,12 +150,16 @@ class Decoder(srd.Decoder): # State machine. if self.state == 'IDLE': + bit = 1 self.edges.append(self.samplenum) - self.bits.append([self.samplenum, 1]) + self.bits.append([self.samplenum, bit]) self.state = 'MID1' self.old_ir = self.ir continue edge = self.edge_type() + if edge == 'e': + self.reset_decoder_state() # Reset state machine upon errors. + continue if self.state == 'MID1': self.state = 'START1' if edge == 's' else 'MID0' bit = None if edge == 's' else 0 @@ -160,17 +174,13 @@ class Decoder(srd.Decoder): if edge == 's': self.state = 'MID0' bit = 0 if edge == 's' else None - else: - raise Exception('Invalid state: %s' % self.state) self.edges.append(self.samplenum) - if bit != None: + if bit is not None: self.bits.append([self.samplenum, bit]) - if len(self.bits) == 14 + 1: + if len(self.bits) == 14: self.handle_bits() - self.edges, self.bits, self.bits_ss_es = [], [], [] - self.state = 'IDLE' + self.reset_decoder_state() self.old_ir = self.ir -