X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fi2c%2Fpd.py;h=f31e33ef85fb38341cb631c82b3dd912dccf7f87;hp=b46fd1de194309457f067d4dc1a1841fdf78d376;hb=d6d8a8a440ea2a81e6ddde33d16bc84d01cdb432;hpb=21cda9512f29947617da45822ab524b1f76f56c1 diff --git a/decoders/i2c/pd.py b/decoders/i2c/pd.py index b46fd1d..f31e33e 100644 --- a/decoders/i2c/pd.py +++ b/decoders/i2c/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2010-2014 Uwe Hermann +## Copyright (C) 2010-2016 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,12 +14,10 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## # TODO: Look into arbitration, collision detection, clock synchronisation, etc. -# TODO: Implement support for 10bit slave addresses. # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). # TODO: Implement support for detecting various bus errors. @@ -63,11 +61,8 @@ proto = { 'DATA WRITE': [9, 'Data write', 'DW'], } -class SamplerateError(Exception): - pass - class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'i2c' name = 'I²C' longname = 'Inter-Integrated Circuit' @@ -75,6 +70,7 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['i2c'] + tags = ['Embedded/industrial'] channels = ( {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, @@ -108,17 +104,17 @@ class Decoder(srd.Decoder): ('data-write', 'Data write'), ) - def __init__(self, **kwargs): + def __init__(self): + self.reset() + + def reset(self): self.samplerate = None - self.ss = self.es = self.byte_ss = -1 - self.samplenum = None + self.ss = self.es = self.ss_byte = -1 self.bitcount = 0 self.databyte = 0 self.wr = -1 self.is_repeat_start = 0 self.state = 'FIND START' - self.oldscl = self.oldsda = 1 - self.oldpins = [1, 1] self.pdu_start = None self.pdu_bits = 0 self.bits = [] @@ -143,25 +139,7 @@ class Decoder(srd.Decoder): def putb(self, data): self.put(self.ss, self.es, self.out_binary, data) - def is_start_condition(self, scl, sda): - # START condition (S): SDA = falling, SCL = high - if (self.oldsda == 1 and sda == 0) and scl == 1: - return True - return False - - def is_data_bit(self, scl, sda): - # Data sampling of receiver: SCL = rising - if self.oldscl == 0 and scl == 1: - return True - return False - - def is_stop_condition(self, scl, sda): - # STOP condition (P): SDA = rising, SCL = high - if (self.oldsda == 0 and sda == 1) and scl == 1: - return True - return False - - def found_start(self, scl, sda): + def handle_start(self, pins): self.ss, self.es = self.samplenum, self.samplenum self.pdu_start = self.samplenum self.pdu_bits = 0 @@ -175,14 +153,17 @@ class Decoder(srd.Decoder): self.bits = [] # Gather 8 bits of data plus the ACK/NACK bit. - def found_address_or_data(self, scl, sda): + def handle_address_or_data(self, pins): + scl, sda = pins + self.pdu_bits += 1 + # Address and data are transmitted MSB-first. self.databyte <<= 1 self.databyte |= sda # Remember the start of the first data/address bit. if self.bitcount == 0: - self.byte_ss = self.samplenum + self.ss_byte = self.samplenum # Store individual bits and their start/end samplenumbers. # In the list, index 0 represents the LSB (I²C transmits MSB-first). @@ -219,12 +200,12 @@ class Decoder(srd.Decoder): cmd = 'DATA READ' bin_class = 2 - self.ss, self.es = self.byte_ss, self.samplenum + self.bitwidth + self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth self.putp(['BITS', self.bits]) self.putp([cmd, d]) - self.putb((bin_class, bytes([d]))) + self.putb([bin_class, bytes([d])]) for bit in self.bits: self.put(bit[1], bit[2], self.out_ann, [5, ['%d' % bit[0]]]) @@ -233,7 +214,7 @@ class Decoder(srd.Decoder): self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth w = ['Write', 'Wr', 'W'] if self.wr else ['Read', 'Rd', 'R'] self.putx([proto[cmd][0], w]) - self.ss, self.es = self.byte_ss, self.samplenum + self.ss, self.es = self.ss_byte, self.samplenum self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d), '%s: %02X' % (proto[cmd][2], d), '%02X' % d]]) @@ -243,7 +224,8 @@ class Decoder(srd.Decoder): self.bits = [] self.state = 'FIND ACK' - def get_ack(self, scl, sda): + def get_ack(self, pins): + scl, sda = pins self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth cmd = 'NACK' if (sda == 1) else 'ACK' self.putp([cmd, None]) @@ -252,11 +234,12 @@ class Decoder(srd.Decoder): # another data byte or a STOP condition next. self.state = 'FIND DATA' - def found_stop(self, scl, sda): + def handle_stop(self, pins): # Meta bitrate - elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1) - bitrate = int(1 / elapsed * self.pdu_bits) - self.put(self.byte_ss, self.samplenum, self.out_bitrate, bitrate) + if self.samplerate: + elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1) + bitrate = int(1 / elapsed * self.pdu_bits) + self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate) cmd = 'STOP' self.ss, self.es = self.samplenum, self.samplenum @@ -267,36 +250,29 @@ class Decoder(srd.Decoder): self.wr = -1 self.bits = [] - def decode(self, ss, es, data): - if not self.samplerate: - raise SamplerateError('Cannot decode without samplerate.') - for (self.samplenum, pins) in data: - - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins, (scl, sda) = pins, pins - - self.pdu_bits += 1 - + def decode(self): + while True: # State machine. if self.state == 'FIND START': - if self.is_start_condition(scl, sda): - self.found_start(scl, sda) + # Wait for a START condition (S): SCL = high, SDA = falling. + self.handle_start(self.wait({0: 'h', 1: 'f'})) elif self.state == 'FIND ADDRESS': - if self.is_data_bit(scl, sda): - self.found_address_or_data(scl, sda) + # Wait for a data bit: SCL = rising. + self.handle_address_or_data(self.wait({0: 'r'})) elif self.state == 'FIND DATA': - if self.is_data_bit(scl, sda): - self.found_address_or_data(scl, sda) - elif self.is_start_condition(scl, sda): - self.found_start(scl, sda) - elif self.is_stop_condition(scl, sda): - self.found_stop(scl, sda) + # Wait for any of the following conditions (or combinations): + # a) Data sampling of receiver: SCL = rising, and/or + # b) START condition (S): SCL = high, SDA = falling, and/or + # c) STOP condition (P): SCL = high, SDA = rising + pins = self.wait([{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}]) + + # Check which of the condition(s) matched and handle them. + if self.matched[0]: + self.handle_address_or_data(pins) + elif self.matched[1]: + self.handle_start(pins) + elif self.matched[2]: + self.handle_stop(pins) elif self.state == 'FIND ACK': - if self.is_data_bit(scl, sda): - self.get_ack(scl, sda) - - # Save current SDA/SCL values for the next round. - self.oldscl, self.oldsda = scl, sda - + # Wait for a data/ack bit: SCL = rising. + self.get_ack(self.wait({0: 'r'}))