X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fi2c%2Fpd.py;h=6172fb438c50f9295c8786fe47d0d9672e4e4f85;hp=6c505e02c2ad1c864150cd2667d35a41b874a050;hb=4539e9ca58966ce3c9cad4801b16c315e86ace01;hpb=be6733ca41275b59a5e240ff104f2a16ad3828d3 diff --git a/decoders/i2c/pd.py b/decoders/i2c/pd.py index 6c505e0..6172fb4 100644 --- a/decoders/i2c/pd.py +++ b/decoders/i2c/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2010-2013 Uwe Hermann +## Copyright (C) 2010-2016 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,12 +14,9 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## -# I2C protocol decoder - # TODO: Look into arbitration, collision detection, clock synchronisation, etc. # TODO: Implement support for 10bit slave addresses. # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). @@ -28,12 +25,12 @@ import sigrokdecode as srd ''' -Protocol output format: +OUTPUT_PYTHON format: -I2C packet: -[, ] +Packet: +[, ] - is one of: +: - 'START' (START condition) - 'START REPEAT' (Repeated START condition) - 'ADDRESS READ' (Slave address, read) @@ -43,11 +40,12 @@ I2C packet: - 'STOP' (STOP condition) - 'ACK' (ACK bit) - 'NACK' (NACK bit) + - 'BITS' (: list of data/address bits and their ss/es numbers) - is the data or address byte associated with the 'ADDRESS*' and 'DATA*' + is the data or address byte associated with the 'ADDRESS*' and 'DATA*' command. Slave addresses do not include bit 0 (the READ/WRITE indication bit). For example, a slave address field could be 0x51 (instead of 0xa2). -For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' is None. +For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' is None. ''' # CMD: [annotation-type-index, long annotation, short annotation] @@ -57,41 +55,51 @@ proto = { 'STOP': [2, 'Stop', 'P'], 'ACK': [3, 'ACK', 'A'], 'NACK': [4, 'NACK', 'N'], - 'ADDRESS READ': [5, 'Address read', 'AR'], - 'ADDRESS WRITE': [6, 'Address write', 'AW'], - 'DATA READ': [7, 'Data read', 'DR'], - 'DATA WRITE': [8, 'Data write', 'DW'], + 'BIT': [5, 'Bit', 'B'], + 'ADDRESS READ': [6, 'Address read', 'AR'], + 'ADDRESS WRITE': [7, 'Address write', 'AW'], + 'DATA READ': [8, 'Data read', 'DR'], + 'DATA WRITE': [9, 'Data write', 'DW'], } +class SamplerateError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 3 id = 'i2c' - name = 'I2C' + name = 'I²C' longname = 'Inter-Integrated Circuit' desc = 'Two-wire, multi-master, serial bus.' license = 'gplv2+' inputs = ['logic'] outputs = ['i2c'] - probes = [ + channels = ( {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, - ] - optional_probes = [] - options = { - 'address_format': ['Displayed slave address format', 'shifted'], - } - annotations = [ - ['start', 'Start condition'], - ['repeat-start', 'Repeat start condition'], - ['stop', 'Stop condition'], - ['ack', 'ACK'], - ['nack', 'NACK'], - ['address-read', 'Address read'], - ['address-write', 'Address write'], - ['data-read', 'Data read'], - ['data-write', 'Data write'], - ['warnings', 'Human-readable warnings'], - ] + ) + options = ( + {'id': 'address_format', 'desc': 'Displayed slave address format', + 'default': 'shifted', 'values': ('shifted', 'unshifted')}, + ) + annotations = ( + ('start', 'Start condition'), + ('repeat-start', 'Repeat start condition'), + ('stop', 'Stop condition'), + ('ack', 'ACK'), + ('nack', 'NACK'), + ('bit', 'Data/address bit'), + ('address-read', 'Address read'), + ('address-write', 'Address write'), + ('data-read', 'Data read'), + ('data-write', 'Data write'), + ('warnings', 'Human-readable warnings'), + ) + annotation_rows = ( + ('bits', 'Bits', (5,)), + ('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 6, 7, 8, 9)), + ('warnings', 'Warnings', (10,)), + ) binary = ( ('address-read', 'Address read'), ('address-write', 'Address write'), @@ -99,61 +107,44 @@ class Decoder(srd.Decoder): ('data-write', 'Data write'), ) - def __init__(self, **kwargs): + def __init__(self): self.samplerate = None - self.startsample = -1 - self.samplenum = None + self.ss = self.es = self.ss_byte = -1 self.bitcount = 0 self.databyte = 0 self.wr = -1 self.is_repeat_start = 0 self.state = 'FIND START' - self.oldscl = 1 - self.oldsda = 1 - self.oldpins = [1, 1] self.pdu_start = None self.pdu_bits = 0 + self.bits = [] def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: self.samplerate = value def start(self): - self.out_proto = self.register(srd.OUTPUT_PYTHON) + self.out_python = self.register(srd.OUTPUT_PYTHON) self.out_ann = self.register(srd.OUTPUT_ANN) self.out_binary = self.register(srd.OUTPUT_BINARY) self.out_bitrate = self.register(srd.OUTPUT_META, meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit')) + # Assume that the initial SCL/SDA pin state is high (logic 1). + # This is a good default, since both pins have pullups as per spec. + self.initial_pins = [1, 1] + def putx(self, data): - self.put(self.startsample, self.samplenum, self.out_ann, data) + self.put(self.ss, self.es, self.out_ann, data) def putp(self, data): - self.put(self.startsample, self.samplenum, self.out_proto, data) + self.put(self.ss, self.es, self.out_python, data) def putb(self, data): - self.put(self.startsample, self.samplenum, self.out_binary, data) - - def is_start_condition(self, scl, sda): - # START condition (S): SDA = falling, SCL = high - if (self.oldsda == 1 and sda == 0) and scl == 1: - return True - return False - - def is_data_bit(self, scl, sda): - # Data sampling of receiver: SCL = rising - if self.oldscl == 0 and scl == 1: - return True - return False - - def is_stop_condition(self, scl, sda): - # STOP condition (P): SDA = rising, SCL = high - if (self.oldsda == 0 and sda == 1) and scl == 1: - return True - return False - - def found_start(self, scl, sda): - self.startsample = self.samplenum + self.put(self.ss, self.es, self.out_binary, data) + + def handle_start(self, pins): + self.ss, self.es = self.samplenum, self.samplenum self.pdu_start = self.samplenum self.pdu_bits = 0 cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START' @@ -163,24 +154,35 @@ class Decoder(srd.Decoder): self.bitcount = self.databyte = 0 self.is_repeat_start = 1 self.wr = -1 + self.bits = [] # Gather 8 bits of data plus the ACK/NACK bit. - def found_address_or_data(self, scl, sda): + def handle_address_or_data(self, pins): + scl, sda = pins + self.pdu_bits += 1 + # Address and data are transmitted MSB-first. self.databyte <<= 1 self.databyte |= sda + # Remember the start of the first data/address bit. if self.bitcount == 0: - self.startsample = self.samplenum + self.ss_byte = self.samplenum + + # Store individual bits and their start/end samplenumbers. + # In the list, index 0 represents the LSB (I²C transmits MSB-first). + self.bits.insert(0, [sda, self.samplenum, self.samplenum]) + if self.bitcount > 0: + self.bits[1][2] = self.samplenum + if self.bitcount == 7: + self.bitwidth = self.bits[1][2] - self.bits[2][2] + self.bits[0][2] += self.bitwidth # Return if we haven't collected all 8 + 1 bits, yet. - self.bitcount += 1 - if self.bitcount != 8: + if self.bitcount < 7: + self.bitcount += 1 return - # We triggered on the ACK/NACK bit, but won't report that until later. - self.startsample -= 1 - d = self.databyte if self.state == 'FIND ADDRESS': # The READ/WRITE bit is only in address bytes, not data bytes. @@ -202,18 +204,33 @@ class Decoder(srd.Decoder): cmd = 'DATA READ' bin_class = 2 + self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth + + self.putp(['BITS', self.bits]) self.putp([cmd, d]) + + self.putb([bin_class, bytes([d])]) + + for bit in self.bits: + self.put(bit[1], bit[2], self.out_ann, [5, ['%d' % bit[0]]]) + + if cmd.startswith('ADDRESS'): + self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth + w = ['Write', 'Wr', 'W'] if self.wr else ['Read', 'Rd', 'R'] + self.putx([proto[cmd][0], w]) + self.ss, self.es = self.ss_byte, self.samplenum + self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d), - '%s: %02X' % (proto[cmd][2], d), '%02X' % d]]) - self.putb((bin_class, bytes([d]))) + '%s: %02X' % (proto[cmd][2], d), '%02X' % d]]) # Done with this packet. - self.startsample = -1 self.bitcount = self.databyte = 0 + self.bits = [] self.state = 'FIND ACK' - def get_ack(self, scl, sda): - self.startsample = self.samplenum + def get_ack(self, pins): + scl, sda = pins + self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth cmd = 'NACK' if (sda == 1) else 'ACK' self.putp([cmd, None]) self.putx([proto[cmd][0], proto[cmd][1:]]) @@ -221,55 +238,50 @@ class Decoder(srd.Decoder): # another data byte or a STOP condition next. self.state = 'FIND DATA' - def found_stop(self, scl, sda): + def handle_stop(self, pins): # Meta bitrate elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1) bitrate = int(1 / elapsed * self.pdu_bits) - self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) + self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate) - self.startsample = self.samplenum cmd = 'STOP' + self.ss, self.es = self.samplenum, self.samplenum self.putp([cmd, None]) self.putx([proto[cmd][0], proto[cmd][1:]]) self.state = 'FIND START' self.is_repeat_start = 0 self.wr = -1 + self.bits = [] - def decode(self, ss, es, data): - if self.samplerate is None: - raise Exception("Cannot decode without samplerate.") - for (self.samplenum, pins) in data: - - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins, (scl, sda) = pins, pins + def decode(self): + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') - self.pdu_bits += 1 - - # TODO: Wait until the bus is idle (SDA = SCL = 1) first? + self.wait({}) + while True: # State machine. if self.state == 'FIND START': - if self.is_start_condition(scl, sda): - self.found_start(scl, sda) + # Wait for a START condition (S): SCL = high, SDA = falling. + self.handle_start(self.wait({0: 'h', 1: 'f'})) elif self.state == 'FIND ADDRESS': - if self.is_data_bit(scl, sda): - self.found_address_or_data(scl, sda) + # Wait for a data bit: SCL = rising. + self.handle_address_or_data(self.wait({0: 'r'})) elif self.state == 'FIND DATA': - if self.is_data_bit(scl, sda): - self.found_address_or_data(scl, sda) - elif self.is_start_condition(scl, sda): - self.found_start(scl, sda) - elif self.is_stop_condition(scl, sda): - self.found_stop(scl, sda) + # Wait for any of the following conditions (or combinations): + # a) Data sampling of receiver: SCL = rising, and/or + # b) START condition (S): SCL = high, SDA = falling, and/or + # c) STOP condition (P): SCL = high, SDA = rising + conds = [{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}] + pins = self.wait(conds[:]) # TODO + + # Check which of the condition(s) matched and handle them. + if self.matched[0]: + self.handle_address_or_data(pins) + elif self.matched[1]: + self.handle_start(pins) + elif self.matched[2]: + self.handle_stop(pins) elif self.state == 'FIND ACK': - if self.is_data_bit(scl, sda): - self.get_ack(scl, sda) - else: - raise Exception('Invalid state: %s' % self.state) - - # Save current SDA/SCL values for the next round. - self.oldscl = scl - self.oldsda = sda - + # Wait for a data/ack bit: SCL = rising. + self.get_ack(self.wait({0: 'r'}))