X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fi2c.py;h=cf16d3a28dc0ab86937a170bedba6a22e404e583;hp=f0b32e781d27e20a5af4eb76c79d95ff087c45a4;hb=71071bcfd36bed13b110931a6cc8189a1493dd2a;hpb=3643fc3fe053bf531b4a7618d02c3d92c29f924b diff --git a/decoders/i2c.py b/decoders/i2c.py index f0b32e7..cf16d3a 100644 --- a/decoders/i2c.py +++ b/decoders/i2c.py @@ -1,7 +1,7 @@ ## ## This file is part of the sigrok project. ## -## Copyright (C) 2010 Uwe Hermann +## Copyright (C) 2010-2011 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,6 +39,7 @@ # # START condition (S): SDA = falling, SCL = high # Repeated START condition (Sr): same as S +# Data bit sampling: SCL = rising # STOP condition (P): SDA = rising, SCL = high # # All data bytes on SDA are exactly 8 bits long (transmitted MSB-first). @@ -125,18 +126,37 @@ # 'signals': [{'SCL': }]} # +import sigrok + +# symbols for i2c decoders up the stack +START = 1 +START_REPEAT = 2 +STOP = 3 +ACK = 4 +NACK = 5 +ADDRESS_READ = 6 +ADDRESS_WRITE = 7 +DATA_READ = 8 +DATA_WRITE = 9 + +# States +FIND_START = 0 +FIND_ADDRESS = 1 +FIND_DATA = 2 + class Sample(): def __init__(self, data): self.data = data def probe(self, probe): - s = ord(self.data[probe / 8]) & (1 << (probe % 8)) + s = self.data[probe / 8] & (1 << (probe % 8)) return True if s else False def sampleiter(data, unitsize): for i in range(0, len(data), unitsize): yield(Sample(data[i:i+unitsize])) -class Decoder(): +class Decoder(sigrok.Decoder): + id = 'i2c' name = 'I2C' longname = 'Inter-Integrated Circuit (I2C) bus' desc = 'I2C is a two-wire, multi-master, serial bus.' @@ -156,18 +176,20 @@ class Decoder(): def __init__(self, **kwargs): self.probes = Decoder.probes.copy() + self.output_protocol = None + self.output_annotation = None # TODO: Don't hardcode the number of channels. self.channels = 8 self.samplenum = 0 - self.bitcount = 0 self.databyte = 0 self.wr = -1 self.startsample = -1 - self.IDLE, self.START, self.ADDRESS, self.DATA = range(4) - self.state = self.IDLE + self.is_repeat_start = 0 + + self.state = FIND_START # Get the channel/probe number of the SCL/SDA signals. self.scl_bit = self.probes['scl']['ch'] @@ -178,19 +200,137 @@ class Decoder(): def start(self, metadata): self.unitsize = metadata["unitsize"] - + self.output_protocol = self.output_new(2) + self.output_annotation = self.output_new(1) def report(self): pass - def decode(self, data): - """I2C protocol decoder""" + def is_start_condition(self, scl, sda): + """START condition (S): SDA = falling, SCL = high""" + if (self.oldsda == 1 and sda == 0) and scl == 1: + return True + return False + + def is_data_bit(self, scl, sda): + """Data sampling of receiver: SCL = rising""" + if self.oldscl == 0 and scl == 1: + return True + return False + + def is_stop_condition(self, scl, sda): + """STOP condition (P): SDA = rising, SCL = high""" + if (self.oldsda == 0 and sda == 1) and scl == 1: + return True + return False + + def found_start(self, scl, sda): + if self.is_repeat_start == 1: + out_proto = [ START_REPEAT ] + out_ann = [ "START REPEAT" ] + else: + out_proto = [ START ] + out_ann = [ "START" ] + self.put(self.output_protocol, out_proto) + self.put(self.output_annotation, out_ann) + + self.state = FIND_ADDRESS + self.bitcount = self.databyte = 0 + self.is_repeat_start = 1 + self.wr = -1 + + def found_address_or_data(self, scl, sda): + """Gather 8 bits of data plus the ACK/NACK bit.""" + + if self.startsample == -1: + self.startsample = self.samplenum + self.bitcount += 1 + + # Address and data are transmitted MSB-first. + self.databyte <<= 1 + self.databyte |= sda + + # Return if we haven't collected all 8 + 1 bits, yet. + if self.bitcount != 9: + return [] + + # We received 8 address/data bits and the ACK/NACK bit. + self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here. + + if self.state == FIND_ADDRESS: + d = self.databyte & 0xfe + # The READ/WRITE bit is only in address bytes, not data bytes. + self.wr = 1 if (self.databyte & 1) else 0 + elif self.state == FIND_DATA: + d = self.databyte + else: + # TODO: Error? + pass + + out_proto = [] + out_ann = [] + # TODO: Simplify. + if self.state == FIND_ADDRESS and self.wr == 1: + cmd = ADDRESS_WRITE + ann = 'ADDRESS WRITE' + elif self.state == FIND_ADDRESS and self.wr == 0: + cmd = ADDRESS_READ + ann = 'ADDRESS READ' + elif self.state == FIND_DATA and self.wr == 1: + cmd = DATA_WRITE + ann = 'DATA WRITE' + elif self.state == FIND_DATA and self.wr == 0: + cmd = DATA_READ + ann = 'DATA READ' + out_proto.append( [cmd, d] ) + out_ann.append( ["%s" % ann, "0x%02x" % d] ) + + if sda == 1: + out_proto.append( [NACK] ) + out_ann.append( ["NACK"] ) + else: + out_proto.append( [ACK] ) + out_ann.append( ["ACK"] ) + + self.put(self.output_protocol, out_proto) + self.put(self.output_annotation, out_ann) + + self.bitcount = self.databyte = 0 + self.startsample = -1 + + if self.state == FIND_ADDRESS: + self.state = FIND_DATA + elif self.state == FIND_DATA: + # There could be multiple data bytes in a row. + # So, either find a STOP condition or another data byte next. + pass + + def found_stop(self, scl, sda): + self.put(self.output_protocol, [ STOP ]) + self.put(self.output_annotation, [ "STOP" ]) + + self.state = FIND_START + self.is_repeat_start = 0 + self.wr = -1 - out = [] - o = ack = d = '' + def put(self, output_id, data): + timeoffset = self.timeoffset + ((self.samplenum - self.bitcount) * self.period) + if self.bitcount > 0: + duration = self.bitcount * self.period + else: + duration = self.period + print("**", timeoffset, duration) + super(Decoder, self).put(timeoffset, duration, output_id, data) + + def decode(self, timeoffset, duration, data): + self.timeoffset = timeoffset + self.duration = duration + print("++", timeoffset, duration, len(data)) + # duration of one bit in ps, only valid for this call to decode() + self.period = int(duration / len(data)) # We should accept a list of samples and iterate... - for sample in sampleiter(data["data"], self.unitsize): + for sample in sampleiter(data, self.unitsize): # TODO: Eliminate the need for ord(). s = ord(sample.data) @@ -211,82 +351,26 @@ class Decoder(): # TODO: Wait until the bus is idle (SDA = SCL = 1) first? - # START condition (S): SDA = falling, SCL = high - if (self.oldsda == 1 and sda == 0) and scl == 1: - o = {'type': 'S', 'range': (self.samplenum, self.samplenum), - 'data': None, 'ann': None}, - out.append(o) - self.state = self.ADDRESS - self.bitcount = self.databyte = 0 - - # Data latching by transmitter: SCL = low - elif (scl == 0): - pass # TODO - - # Data sampling of receiver: SCL = rising - elif (self.oldscl == 0 and scl == 1): - if self.startsample == -1: - self.startsample = self.samplenum - self.bitcount += 1 - - # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \ - # (self.samplenum, 8 - bitcount, sda)) - - # Address and data are transmitted MSB-first. - self.databyte <<= 1 - self.databyte |= sda - - if self.bitcount != 9: - continue - - # We received 8 address/data bits and the ACK/NACK bit. - self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here. - ack = (sda == 1) and 'N' or 'A' - d = (self.state == self.ADDRESS) and (self.databyte & 0xfe) or self.databyte - if self.state == self.ADDRESS: - self.wr = (self.databyte & 1) and 1 or 0 - self.state = self.DATA - o = {'type': self.state, - 'range': (self.startsample, self.samplenum - 1), - 'data': d, 'ann': None} - if self.state == self.ADDRESS and self.wr == 1: - o['type'] = 'AW' - elif self.state == self.ADDRESS and self.wr == 0: - o['type'] = 'AR' - elif self.state == self.DATA and self.wr == 1: - o['type'] = 'DW' - elif self.state == self.DATA and self.wr == 0: - o['type'] = 'DR' - out.append(o) - o = {'type': ack, 'range': (self.samplenum, self.samplenum), - 'data': None, 'ann': None} - out.append(o) - self.bitcount = self.databyte = self.startsample = 0 - self.startsample = -1 - - # STOP condition (P): SDA = rising, SCL = high - elif (self.oldsda == 0 and sda == 1) and scl == 1: - o = {'type': 'P', 'range': (self.samplenum, self.samplenum), - 'data': None, 'ann': None}, - out.append(o) - self.state = self.IDLE - self.wr = -1 + # State machine. + if self.state == FIND_START: + if self.is_start_condition(scl, sda): + self.found_start(scl, sda) + elif self.state == FIND_ADDRESS: + if self.is_data_bit(scl, sda): + self.found_address_or_data(scl, sda) + elif self.state == FIND_DATA: + if self.is_data_bit(scl, sda): + self.found_address_or_data(scl, sda) + elif self.is_start_condition(scl, sda): + self.found_start(scl, sda) + elif self.is_stop_condition(scl, sda): + self.found_stop(scl, sda) + else: + # TODO: Error? + pass # Save current SDA/SCL values for the next round. self.oldscl = scl self.oldsda = sda - # TODO: Which output format? - # TODO: How to only output something after the last chunk of data? - if out != []: - sigrok.put(out) - -# Use psyco (if available) as it results in huge performance improvements. -try: - import psyco - psyco.bind(decode) -except ImportError: - pass - -import sigrok