X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fi2c.py;h=967899ed5c24d282e86809403a0aa2b5f2398ba0;hp=2301c3c4dfbcf19fc1436d2917da21108005d338;hb=9a12a6e7af3d7091d8e35dd1c731402cb80a01b0;hpb=c4262fd6b2f8ef540b8cc93ac61956d89062d2be diff --git a/decoders/i2c.py b/decoders/i2c.py index 2301c3c..967899e 100644 --- a/decoders/i2c.py +++ b/decoders/i2c.py @@ -65,81 +65,62 @@ # TODO: Implement support for 7bit and 10bit slave addresses. # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0). # TODO: Implement support for detecting various bus errors. - -# -# I2C output format: -# -# The output consists of a (Python) list of I2C "packets", each of which -# has an (implicit) index number (its index in the list). -# Each packet consists of a Python dict with certain key/value pairs. -# -# TODO: Make this a list later instead of a dict? -# -# 'type': (string) -# - 'S' (START condition) -# - 'Sr' (Repeated START) -# - 'AR' (Address, read) -# - 'AW' (Address, write) -# - 'DR' (Data, read) -# - 'DW' (Data, write) -# - 'P' (STOP condition) -# 'range': (tuple of 2 integers, the min/max samplenumber of this range) -# - (min, max) -# - min/max can also be identical. -# 'data': (actual data as integer ???) TODO: This can be very variable... -# 'ann': (string; additional annotations / comments) -# -# Example output: -# [{'type': 'S', 'range': (150, 160), 'data': None, 'ann': 'Foobar'}, -# {'type': 'AW', 'range': (200, 300), 'data': 0x50, 'ann': 'Slave 4'}, -# {'type': 'DW', 'range': (310, 370), 'data': 0x00, 'ann': 'Init cmd'}, -# {'type': 'AR', 'range': (500, 560), 'data': 0x50, 'ann': 'Get stat'}, -# {'type': 'DR', 'range': (580, 640), 'data': 0xfe, 'ann': 'OK'}, -# {'type': 'P', 'range': (650, 660), 'data': None, 'ann': None}] -# -# Possible other events: -# - Error event in case protocol looks broken: -# [{'type': 'ERROR', 'range': (min, max), -# 'data': TODO, 'ann': 'This is not a Microchip 24XX64 EEPROM'}, -# [{'type': 'ERROR', 'range': (min, max), -# 'data': TODO, 'ann': 'TODO'}, -# - TODO: Make list of possible errors accessible as metadata? -# # TODO: I2C address of slaves. # TODO: Handle multiple different I2C devices on same bus # -> we need to decode multiple protocols at the same time. -# TODO: range: Always contiguous? Splitted ranges? Multiple per event? -# # -# I2C input format: +# I2C protocol output format: # -# signals: -# [[id, channel, description], ...] # TODO +# The protocol output consists of a (Python) list of I2C "packets", each of +# which is of the form # -# Example: -# {'id': 'SCL', 'ch': 5, 'desc': 'Serial clock line'} -# {'id': 'SDA', 'ch': 7, 'desc': 'Serial data line'} -# ... +# [, , ] # -# {'inbuf': [...], -# 'signals': [{'SCL': }]} +# is one of: +# - 'START' (START condition) +# - 'START_REPEAT' (Repeated START) +# - 'ADDRESS_READ' (Slave address, read) +# - 'ADDRESS_WRITE' (Slave address, write) +# - 'DATA_READ' (Data, read) +# - 'DATA_WRITE' (Data, write) +# - 'STOP' (STOP condition) +# +# is the data or address byte associated with the ADDRESS_* and DATA_* +# command. For START, START_REPEAT and STOP, this is None. +# +# is either 'ACK' or 'NACK', but may also be None. # -class Sample(): - def __init__(self, data): - self.data = data - def probe(self, probe): - s = ord(self.data[probe / 8]) & (1 << (probe % 8)) - return True if s else False - -def sampleiter(data, unitsize): - for i in range(0, len(data), unitsize): - yield(Sample(data[i:i+unitsize])) - -class Decoder(): +import sigrokdecode as srd + +# Annotation feed formats +ANN_SHIFTED = 0 +ANN_SHIFTED_SHORT = 1 +ANN_RAW = 2 + +# Values are verbose and short annotation, respectively. +protocol = { + 'START': ['START', 'S'], + 'START_REPEAT': ['START REPEAT', 'Sr'], + 'STOP': ['STOP', 'P'], + 'ACK': ['ACK', 'A'], + 'NACK': ['NACK', 'N'], + 'ADDRESS_READ': ['ADDRESS READ', 'AR'], + 'ADDRESS_WRITE': ['ADDRESS WRITE', 'AW'], + 'DATA_READ': ['DATA READ', 'DR'], + 'DATA_WRITE': ['DATA WRITE', 'DW'], +} + +# States +FIND_START = 0 +FIND_ADDRESS = 1 +FIND_DATA = 2 + +class Decoder(srd.Decoder): + id = 'i2c' name = 'I2C' - longname = 'Inter-Integrated Circuit (I2C) bus' + longname = 'Inter-Integrated Circuit' desc = 'I2C is a two-wire, multi-master, serial bus.' longdesc = '...' author = 'Uwe Hermann' @@ -147,79 +128,78 @@ class Decoder(): license = 'gplv2+' inputs = ['logic'] outputs = ['i2c'] - probes = { - 'scl': {'ch': 0, 'name': 'SCL', 'desc': 'Serial clock line'}, - 'sda': {'ch': 1, 'name': 'SDA', 'desc': 'Serial data line'}, - } + probes = [ + {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'}, + {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'}, + ] options = { 'address-space': ['Address space (in bits)', 7], } + annotations = [ + # ANN_SHIFTED + ['7-bit shifted hex', + 'Read/write bit shifted out from the 8-bit I2C slave address'], + # ANN_SHIFTED_SHORT + ['7-bit shifted hex (short)', + 'Read/write bit shifted out from the 8-bit I2C slave address'], + # ANN_RAW + ['Raw hex', 'Unaltered raw data'], + ] def __init__(self, **kwargs): - self.probes = Decoder.probes.copy() - - # TODO: Don't hardcode the number of channels. - self.channels = 8 - - self.samplenum = 0 + self.samplecnt = 0 self.bitcount = 0 self.databyte = 0 self.wr = -1 self.startsample = -1 self.is_repeat_start = 0 - - self.FIND_START, self.FIND_ADDRESS, self.FIND_DATA = range(3) - self.state = self.FIND_START - - # Get the channel/probe number of the SCL/SDA signals. - self.scl_bit = self.probes['scl']['ch'] - self.sda_bit = self.probes['sda']['ch'] - + self.state = FIND_START self.oldscl = None self.oldsda = None def start(self, metadata): - self.unitsize = metadata["unitsize"] + self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c') + self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c') def report(self): pass def is_start_condition(self, scl, sda): - """START condition (S): SDA = falling, SCL = high""" + # START condition (S): SDA = falling, SCL = high if (self.oldsda == 1 and sda == 0) and scl == 1: return True return False def is_data_bit(self, scl, sda): - """Data sampling of receiver: SCL = rising""" + # Data sampling of receiver: SCL = rising if self.oldscl == 0 and scl == 1: return True return False def is_stop_condition(self, scl, sda): - """STOP condition (P): SDA = rising, SCL = high""" + # STOP condition (P): SDA = rising, SCL = high if (self.oldsda == 0 and sda == 1) and scl == 1: return True return False - def find_start(self, scl, sda): - out = [] - # o = {'type': 'S', 'range': (self.samplenum, self.samplenum), - # 'data': None, 'ann': None}, - o = (self.is_repeat_start == 1) and 'Sr' or 'S' - out.append(o) - self.state = self.FIND_ADDRESS + def found_start(self, scl, sda): + cmd = 'START_REPEAT' if (self.is_repeat_start == 1) else 'START' + + self.put(self.out_proto, [cmd, None, None]) + self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]]) + self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]]) + + self.state = FIND_ADDRESS self.bitcount = self.databyte = 0 self.is_repeat_start = 1 self.wr = -1 - return out - def find_address_or_data(self, scl, sda): - """Gather 8 bits of data plus the ACK/NACK bit.""" - out = o = [] + def found_address_or_data(self, scl, sda): + # Gather 8 bits of data plus the ACK/NACK bit. if self.startsample == -1: - self.startsample = self.samplenum + # TODO: Should be samplenum, as received from the feed. + self.startsample = self.samplecnt self.bitcount += 1 # Address and data are transmitted MSB-first. @@ -228,112 +208,93 @@ class Decoder(): # Return if we haven't collected all 8 + 1 bits, yet. if self.bitcount != 9: - return [] + return + + # Send raw output annotation before we start shifting out + # read/write and ack/nack bits. + self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]]) # We received 8 address/data bits and the ACK/NACK bit. self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here. - ack = (sda == 1) and 'N' or 'A' - - if self.state == self.FIND_ADDRESS: - d = self.databyte & 0xfe + if self.state == FIND_ADDRESS: # The READ/WRITE bit is only in address bytes, not data bytes. - self.wr = (self.databyte & 1) and 1 or 0 - elif self.state == self.FIND_DATA: + self.wr = 0 if (self.databyte & 1) else 1 + d = self.databyte >> 1 + elif self.state == FIND_DATA: d = self.databyte else: # TODO: Error? pass - # o = {'type': self.state, - # 'range': (self.startsample, self.samplenum - 1), - # 'data': d, 'ann': None} + # Last bit that came in was the ACK/NACK bit (1 = NACK). + ack_bit = 'NACK' if (sda == 1) else 'ACK' - o = {'data': "0x%02x" % d} + if self.state == FIND_ADDRESS and self.wr == 1: + cmd = 'ADDRESS_WRITE' + elif self.state == FIND_ADDRESS and self.wr == 0: + cmd = 'ADDRESS_READ' + elif self.state == FIND_DATA and self.wr == 1: + cmd = 'DATA_WRITE' + elif self.state == FIND_DATA and self.wr == 0: + cmd = 'DATA_READ' - # TODO: Simplify. - if self.state == self.FIND_ADDRESS and self.wr == 1: - o['type'] = 'AW' - elif self.state == self.FIND_ADDRESS and self.wr == 0: - o['type'] = 'AR' - elif self.state == self.FIND_DATA and self.wr == 1: - o['type'] = 'DW' - elif self.state == self.FIND_DATA and self.wr == 0: - o['type'] = 'DR' + self.put(self.out_proto, [cmd, d, ack_bit]) + self.put(self.out_ann, [ANN_SHIFTED, + [protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]]) + self.put(self.out_ann, [ANN_SHIFTED_SHORT, + [protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]]) - out.append(o) - - # o = {'type': ack, 'range': (self.samplenum, self.samplenum), - # 'data': None, 'ann': None} - o = ack - out.append(o) self.bitcount = self.databyte = 0 self.startsample = -1 - if self.state == self.FIND_ADDRESS: - self.state = self.FIND_DATA - elif self.state == self.FIND_DATA: + if self.state == FIND_ADDRESS: + self.state = FIND_DATA + elif self.state == FIND_DATA: # There could be multiple data bytes in a row. # So, either find a STOP condition or another data byte next. pass - return out - - def find_stop(self, scl, sda): - out = o = [] + def found_stop(self, scl, sda): + self.put(self.out_proto, ['STOP', None, None]) + self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]]) + self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]]) - # o = {'type': 'P', 'range': (self.samplenum, self.samplenum), - # 'data': None, 'ann': None}, - o = 'P' - out.append(o) - self.state = self.FIND_START + self.state = FIND_START self.is_repeat_start = 0 self.wr = -1 - return out + def put(self, output_id, data): + # Inject sample range into the call up to sigrok. + # TODO: 0-0 sample range for now. + super(Decoder, self).put(0, 0, output_id, data) - def decode(self, data): - """I2C protocol decoder""" - - out = [] - o = ack = d = '' - - # We should accept a list of samples and iterate... - for sample in sampleiter(data["data"], self.unitsize): - - # TODO: Eliminate the need for ord(). - s = ord(sample.data) - - # TODO: Start counting at 0 or 1? - self.samplenum += 1 + def decode(self, timeoffset, duration, data): + for samplenum, (scl, sda) in data: + self.samplecnt += 1 # First sample: Save SCL/SDA value. if self.oldscl == None: - # Get SCL/SDA bit values (0/1 for low/high) of the first sample. - self.oldscl = (s & (1 << self.scl_bit)) >> self.scl_bit - self.oldsda = (s & (1 << self.sda_bit)) >> self.sda_bit + self.oldscl = scl + self.oldsda = sda continue - # Get SCL/SDA bit values (0/1 for low/high). - scl = (s & (1 << self.scl_bit)) >> self.scl_bit - sda = (s & (1 << self.sda_bit)) >> self.sda_bit - # TODO: Wait until the bus is idle (SDA = SCL = 1) first? # State machine. - if self.state == self.FIND_START: + if self.state == FIND_START: if self.is_start_condition(scl, sda): - out += self.find_start(scl, sda) - elif self.state == self.FIND_ADDRESS: + self.found_start(scl, sda) + elif self.state == FIND_ADDRESS: if self.is_data_bit(scl, sda): - out += self.find_address_or_data(scl, sda) - elif self.state == self.FIND_DATA: + self.found_address_or_data(scl, sda) + elif self.state == FIND_DATA: if self.is_data_bit(scl, sda): - out += self.find_address_or_data(scl, sda) + self.found_address_or_data(scl, sda) elif self.is_start_condition(scl, sda): - out += self.find_start(scl, sda) + self.found_start(scl, sda) elif self.is_stop_condition(scl, sda): - out += self.find_stop(scl, sda) + self.found_stop(scl, sda) else: # TODO: Error? pass @@ -342,15 +303,3 @@ class Decoder(): self.oldscl = scl self.oldsda = sda - if out != []: - sigrok.put(out) - -# Use psyco (if available) as it results in huge performance improvements. -try: - import psyco - psyco.bind(decode) -except ImportError: - pass - -import sigrok -