X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fenc28j60%2Fpd.py;h=f7a6625a22c7b58602895dbe44cf1130d7ae5126;hp=f2b8db793ee415db9c8fb681badb5002df0a5827;hb=ff73d589b60677cf405d8e6af8810c849595fd7a;hpb=acc08e512309a2d917045be2f9f2e46f6c5d5d99 diff --git a/decoders/enc28j60/pd.py b/decoders/enc28j60/pd.py index f2b8db7..f7a6625 100644 --- a/decoders/enc28j60/pd.py +++ b/decoders/enc28j60/pd.py @@ -22,6 +22,7 @@ ## SOFTWARE. import sigrokdecode as srd +from .lists import * OPCODE_MASK = 0b11100000 REG_ADDR_MASK = 0b00011111 @@ -43,145 +44,6 @@ REG_ADDR_ECON1 = 0x1F BIT_ECON1_BSEL0 = 0b00000001 BIT_ECON1_BSEL1 = 0b00000010 -REGS = [ - [ - 'ERDPTL', - 'ERDPTH', - 'EWRPTL', - 'EWRPTH', - 'ETXSTL', - 'ETXSTH', - 'ETXNDL', - 'ETXNDH', - 'ERXSTL', - 'ERXSTH', - 'ERXNDL', - 'ERXNDH', - 'ERXRDPTL', - 'ERXRDPTH', - 'ERXWRPTL', - 'ERXWRPTH', - 'EDMASTL', - 'EDMASTH', - 'EDMANDL', - 'EDMANDH', - 'EDMADSTL', - 'EDMADSTH', - 'EDMACSL', - 'EDMACSH', - '—', - '—', - 'Reserved', - 'EIE', - 'EIR', - 'ESTAT', - 'ECON2', - 'ECON1', - ], - [ - 'EHT0', - 'EHT1', - 'EHT2', - 'EHT3', - 'EHT4', - 'EHT5', - 'EHT6', - 'EHT7', - 'EPMM0', - 'EPMM1', - 'EPMM2', - 'EPMM3', - 'EPMM4', - 'EPMM5', - 'EPMM6', - 'EPMM7', - 'EPMCSL', - 'EPMCSH', - '—', - '—', - 'EPMOL', - 'EPMOH', - 'Reserved', - 'Reserved', - 'ERXFCON', - 'EPKTCNT', - 'Reserved', - 'EIE', - 'EIR', - 'ESTAT', - 'ECON2', - 'ECON1', - ], - [ - 'MACON1', - 'Reserved', - 'MACON3', - 'MACON4', - 'MABBIPG', - '—', - 'MAIPGL', - 'MAIPGH', - 'MACLCON1', - 'MACLCON2', - 'MAMXFLL', - 'MAMXFLH', - 'Reserved', - 'Reserved', - 'Reserved', - '—', - 'Reserved', - 'Reserved', - 'MICMD', - '—', - 'MIREGADR', - 'Reserved', - 'MIWRL', - 'MIWRH', - 'MIRDL', - 'MIRDH', - 'Reserved', - 'EIE', - 'EIR', - 'ESTAT', - 'ECON2', - 'ECON1', - ], - [ - 'MAADR5', - 'MAADR6', - 'MAADR3', - 'MAADR4', - 'MAADR1', - 'MAADR2', - 'EBSTSD', - 'EBSTCON', - 'EBSTCSL', - 'EBSTCSH', - 'MISTAT', - '—', - '—', - '—', - '—', - '—', - '—', - '—', - 'EREVID', - '—', - '—', - 'ECOCON', - 'Reserved', - 'EFLOCON', - 'EPAUSL', - 'EPAUSH', - 'Reserved', - 'EIE', - 'EIR', - 'ESTAT', - 'ECON2', - 'ECON1', - ], -] - class Decoder(srd.Decoder): api_version = 3 id = 'enc28j60' @@ -190,7 +52,7 @@ class Decoder(srd.Decoder): desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.' license = 'mit' inputs = ['spi'] - outputs = ['enc28j60'] + outputs = [] tags = ['Embedded/industrial', 'Networking'] annotations = ( ('rcr', 'Read Control Register'), @@ -218,14 +80,22 @@ class Decoder(srd.Decoder): self.mosi = [] self.miso = [] self.ranges = [] - self.command_start = None - self.command_end = None + self.cmd_ss = None + self.cmd_es = None + self.range_ss = None + self.range_es = None self.active = False self.bsel0 = None self.bsel1 = None def start(self): - self.ann = self.register(srd.OUTPUT_ANN) + self.out_ann = self.register(srd.OUTPUT_ANN) + + def putc(self, data): + self.put(self.cmd_ss, self.cmd_es, self.out_ann, data) + + def putr(self, data): + self.put(self.range_ss, self.range_es, self.out_ann, data) def _process_command(self): if len(self.mosi) == 0: @@ -256,68 +126,42 @@ class Decoder(srd.Decoder): reg_addr = self.mosi[0] & REG_ADDR_MASK reg_name = self._get_register_name(reg_addr) + self.range_ss, self.range_es = self.cmd_ss, self.ranges[1][0] + if reg_name is None: # We don't know the bank we're in yet. - self.put(self.command_start, self.ranges[1][0], self.ann, [ - ANN_REG_ADDR, - [ - 'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr), - '?:{0:02X}'.format(reg_addr), - ]]) - self.put(self.command_start, self.ranges[1][0], self.ann, [ - ANN_WARNING, - [ - 'Warning: Register bank not known yet.', - 'Warning', - ]]) + self.putr([ANN_REG_ADDR, [ + 'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr), + '?:{0:02X}'.format(reg_addr)]]) + self.putr([ANN_WARNING, ['Warning: Register bank not known yet.', + 'Warning']]) else: - self.put(self.command_start, self.ranges[1][0], self.ann, [ - ANN_REG_ADDR, - [ - 'Reg {0}'.format(reg_name), - '{0}'.format(reg_name), - ]]) + self.putr([ANN_REG_ADDR, ['Reg {0}'.format(reg_name), + '{0}'.format(reg_name)]]) if (reg_name == '-') or (reg_name == 'Reserved'): - self.put(self.command_start, self.ranges[1][0], self.ann, [ - ANN_WARNING, - [ - 'Warning: Invalid register accessed.', - 'Warning', - ]]) + self.putr([ANN_WARNING, ['Warning: Invalid register accessed.', + 'Warning']]) def _put_data_byte(self, data, byte_index, binary=False): + self.range_ss = self.ranges[byte_index][0] if byte_index == len(self.mosi) - 1: - end_sample = self.command_end + self.range_es = self.cmd_es else: - end_sample = self.ranges[byte_index + 1][0] + self.range_es = self.ranges[byte_index + 1][0] if binary: - self.put(self.ranges[byte_index][0], end_sample, self.ann, [ - ANN_DATA, - [ - 'Data 0b{0:08b}'.format(data), - '{0:08b}'.format(data), - ]]) + self.putr([ANN_DATA, ['Data 0b{0:08b}'.format(data), + '{0:08b}'.format(data)]]) else: - self.put(self.ranges[byte_index][0], end_sample, self.ann, [ - ANN_DATA, - [ - 'Data 0x{0:02X}'.format(data), - '{0:02X}'.format(data), - ]]) + self.putr([ANN_DATA, ['Data 0x{0:02X}'.format(data), + '{0:02X}'.format(data)]]) def _put_command_warning(self, reason): - self.put(self.command_start, self.command_end, self.ann, [ - ANN_WARNING, - [ - 'Warning: {0}'.format(reason), - 'Warning', - ]]) + self.putc([ANN_WARNING, ['Warning: {0}'.format(reason), 'Warning']]) def _process_rcr(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_RCR, ['Read Control Register', 'RCR']]) + self.putc([ANN_RCR, ['Read Control Register', 'RCR']]) if (len(self.mosi) != 2) and (len(self.mosi) != 3): self._put_command_warning('Invalid command length.') @@ -344,12 +188,8 @@ class Decoder(srd.Decoder): if len(self.mosi) == 2: self._put_data_byte(self.miso[1], 1) else: - self.put(self.ranges[1][0], self.ranges[2][0], self.ann, [ - ANN_DATA, - [ - 'Dummy Byte', - 'Dummy', - ]]) + self.range_ss, self.range_es = self.ranges[1][0], self.ranges[2][0] + self.putr([ANN_DATA, ['Dummy Byte', 'Dummy']]) self._put_data_byte(self.miso[2], 2) def _process_rbm(self): @@ -357,20 +197,14 @@ class Decoder(srd.Decoder): self._put_command_warning('Invalid header byte.') return - self.put(self.command_start, self.command_end, self.ann, [ - ANN_RBM, - [ - 'Read Buffer Memory: Length {0}'.format( - len(self.mosi) - 1), - 'RBM', - ]]) + self.putc([ANN_RBM, ['Read Buffer Memory: Length {0}'.format( + len(self.mosi) - 1), 'RBM']]) for i in range(1, len(self.miso)): self._put_data_byte(self.miso[i], i) def _process_wcr(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_WCR, ['Write Control Register', 'WCR']]) + self.putc([ANN_WCR, ['Write Control Register', 'WCR']]) if len(self.mosi) != 2: self._put_command_warning('Invalid command length.') @@ -388,20 +222,14 @@ class Decoder(srd.Decoder): self._put_command_warning('Invalid header byte.') return - self.put(self.command_start, self.command_end, self.ann, [ - ANN_WBM, - [ - 'Write Buffer Memory: Length {0}'.format( - len(self.mosi) - 1), - 'WBM', - ]]) + self.putc([ANN_WBM, ['Write Buffer Memory: Length {0}'.format( + len(self.mosi) - 1), 'WBM']]) for i in range(1, len(self.mosi)): self._put_data_byte(self.mosi[i], i) def _process_bfc(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_BFC, ['Bit Field Clear', 'BFC']]) + self.putc([ANN_BFC, ['Bit Field Clear', 'BFC']]) if len(self.mosi) != 2: self._put_command_warning('Invalid command length.') @@ -417,8 +245,7 @@ class Decoder(srd.Decoder): self.bsel1 = 0 def _process_bfs(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_BFS, ['Bit Field Set', 'BFS']]) + self.putc([ANN_BFS, ['Bit Field Set', 'BFS']]) if len(self.mosi) != 2: self._put_command_warning('Invalid command length.') @@ -434,8 +261,7 @@ class Decoder(srd.Decoder): self.bsel1 = 1 def _process_src(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_SRC, ['System Reset Command', 'SRC']]) + self.putc([ANN_SRC, ['System Reset Command', 'SRC']]) if len(self.mosi) != 1: self._put_command_warning('Invalid command length.') @@ -452,13 +278,13 @@ class Decoder(srd.Decoder): if new_cs == 0: self.active = True - self.command_start = ss + self.cmd_ss = ss self.mosi = [] self.miso = [] self.ranges = [] elif new_cs == 1: if self.active: - self.command_end = es + self.cmd_es = es self._process_command() elif ptype == 'DATA': mosi, miso = data1, data2