X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fenc28j60%2Fpd.py;h=d1a601f220f8a86ff8ceb7c63bdc24c6472da55b;hp=a33f5b0fb48317f2f9cafa6d3fde5f8eac25c695;hb=72db471edc03396ac2d0e3ffd490984617978346;hpb=2df02753c44356b8d8b017a0be027a2e2ca6a35c diff --git a/decoders/enc28j60/pd.py b/decoders/enc28j60/pd.py index a33f5b0..d1a601f 100644 --- a/decoders/enc28j60/pd.py +++ b/decoders/enc28j60/pd.py @@ -22,6 +22,7 @@ ## SOFTWARE. import sigrokdecode as srd +from .lists import * OPCODE_MASK = 0b11100000 REG_ADDR_MASK = 0b00011111 @@ -36,162 +37,13 @@ OPCODE_HANDLERS = { 0b11100000: '_process_src', } -ANN_RCR = 0 -ANN_RBM = 1 -ANN_WCR = 2 -ANN_WBM = 3 -ANN_BFS = 4 -ANN_BFC = 5 -ANN_SRC = 6 - -ANN_DATA = 7 -ANN_REG_ADDR = 8 - -ANN_WARNING = 9 +(ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC, ANN_DATA, +ANN_REG_ADDR, ANN_WARNING) = range(10) REG_ADDR_ECON1 = 0x1F BIT_ECON1_BSEL0 = 0b00000001 BIT_ECON1_BSEL1 = 0b00000010 -REGS = [ - [ - 'ERDPTL', - 'ERDPTH', - 'EWRPTL', - 'EWRPTH', - 'ETXSTL', - 'ETXSTH', - 'ETXNDL', - 'ETXNDH', - 'ERXSTL', - 'ERXSTH', - 'ERXNDL', - 'ERXNDH', - 'ERXRDPTL', - 'ERXRDPTH', - 'ERXWRPTL', - 'ERXWRPTH', - 'EDMASTL', - 'EDMASTH', - 'EDMANDL', - 'EDMANDH', - 'EDMADSTL', - 'EDMADSTH', - 'EDMACSL', - 'EDMACSH', - '—', - '—', - 'Reserved', - 'EIE', - 'EIR', - 'ESTAT', - 'ECON2', - 'ECON1', - ], - [ - 'EHT0', - 'EHT1', - 'EHT2', - 'EHT3', - 'EHT4', - 'EHT5', - 'EHT6', - 'EHT7', - 'EPMM0', - 'EPMM1', - 'EPMM2', - 'EPMM3', - 'EPMM4', - 'EPMM5', - 'EPMM6', - 'EPMM7', - 'EPMCSL', - 'EPMCSH', - '—', - '—', - 'EPMOL', - 'EPMOH', - 'Reserved', - 'Reserved', - 'ERXFCON', - 'EPKTCNT', - 'Reserved', - 'EIE', - 'EIR', - 'ESTAT', - 'ECON2', - 'ECON1', - ], - [ - 'MACON1', - 'Reserved', - 'MACON3', - 'MACON4', - 'MABBIPG', - '—', - 'MAIPGL', - 'MAIPGH', - 'MACLCON1', - 'MACLCON2', - 'MAMXFLL', - 'MAMXFLH', - 'Reserved', - 'Reserved', - 'Reserved', - '—', - 'Reserved', - 'Reserved', - 'MICMD', - '—', - 'MIREGADR', - 'Reserved', - 'MIWRL', - 'MIWRH', - 'MIRDL', - 'MIRDH', - 'Reserved', - 'EIE', - 'EIR', - 'ESTAT', - 'ECON2', - 'ECON1', - ], - [ - 'MAADR5', - 'MAADR6', - 'MAADR3', - 'MAADR4', - 'MAADR1', - 'MAADR2', - 'EBSTSD', - 'EBSTCON', - 'EBSTCSL', - 'EBSTCSH', - 'MISTAT', - '—', - '—', - '—', - '—', - '—', - '—', - '—', - 'EREVID', - '—', - '—', - 'ECOCON', - 'Reserved', - 'EFLOCON', - 'EPAUSL', - 'EPAUSH', - 'Reserved', - 'EIE', - 'EIR', - 'ESTAT', - 'ECON2', - 'ECON1', - ], -] - class Decoder(srd.Decoder): api_version = 3 id = 'enc28j60' @@ -200,7 +52,7 @@ class Decoder(srd.Decoder): desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.' license = 'mit' inputs = ['spi'] - outputs = ['enc28j60'] + outputs = [] tags = ['Embedded/industrial', 'Networking'] annotations = ( ('rcr', 'Read Control Register'), @@ -228,8 +80,8 @@ class Decoder(srd.Decoder): self.mosi = [] self.miso = [] self.ranges = [] - self.command_start = None - self.command_end = None + self.cmd_ss = None + self.cmd_es = None self.active = False self.bsel0 = None self.bsel1 = None @@ -237,6 +89,9 @@ class Decoder(srd.Decoder): def start(self): self.ann = self.register(srd.OUTPUT_ANN) + def putc(self, data): + self.put(self.cmd_ss, self.cmd_es, self.ann, data) + def _process_command(self): if len(self.mosi) == 0: self.active = False @@ -266,22 +121,24 @@ class Decoder(srd.Decoder): reg_addr = self.mosi[0] & REG_ADDR_MASK reg_name = self._get_register_name(reg_addr) + ss, es = self.cmd_ss, self.ranges[1][0] + if reg_name is None: # We don't know the bank we're in yet. - self.put(self.command_start, self.ranges[1][0], self.ann, [ + self.put(ss, es, self.ann, [ ANN_REG_ADDR, [ 'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr), '?:{0:02X}'.format(reg_addr), ]]) - self.put(self.command_start, self.ranges[1][0], self.ann, [ + self.put(ss, es, self.ann, [ ANN_WARNING, [ 'Warning: Register bank not known yet.', 'Warning', ]]) else: - self.put(self.command_start, self.ranges[1][0], self.ann, [ + self.put(ss, es, self.ann, [ ANN_REG_ADDR, [ 'Reg {0}'.format(reg_name), @@ -289,7 +146,7 @@ class Decoder(srd.Decoder): ]]) if (reg_name == '-') or (reg_name == 'Reserved'): - self.put(self.command_start, self.ranges[1][0], self.ann, [ + self.put(ss, es, self.ann, [ ANN_WARNING, [ 'Warning: Invalid register accessed.', @@ -297,20 +154,21 @@ class Decoder(srd.Decoder): ]]) def _put_data_byte(self, data, byte_index, binary=False): + ss = self.ranges[byte_index][0] if byte_index == len(self.mosi) - 1: - end_sample = self.command_end + es = self.cmd_es else: - end_sample = self.ranges[byte_index + 1][0] + es = self.ranges[byte_index + 1][0] if binary: - self.put(self.ranges[byte_index][0], end_sample, self.ann, [ + self.put(ss, es, self.ann, [ ANN_DATA, [ 'Data 0b{0:08b}'.format(data), '{0:08b}'.format(data), ]]) else: - self.put(self.ranges[byte_index][0], end_sample, self.ann, [ + self.put(ss, es, self.ann, [ ANN_DATA, [ 'Data 0x{0:02X}'.format(data), @@ -318,7 +176,7 @@ class Decoder(srd.Decoder): ]]) def _put_command_warning(self, reason): - self.put(self.command_start, self.command_end, self.ann, [ + self.putc([ ANN_WARNING, [ 'Warning: {0}'.format(reason), @@ -326,8 +184,7 @@ class Decoder(srd.Decoder): ]]) def _process_rcr(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_RCR, ['Read Control Register', 'RCR']]) + self.putc([ANN_RCR, ['Read Control Register', 'RCR']]) if (len(self.mosi) != 2) and (len(self.mosi) != 3): self._put_command_warning('Invalid command length.') @@ -354,7 +211,8 @@ class Decoder(srd.Decoder): if len(self.mosi) == 2: self._put_data_byte(self.miso[1], 1) else: - self.put(self.ranges[1][0], self.ranges[2][0], self.ann, [ + ss, es = self.ranges[1][0], self.ranges[2][0] + self.put(ss, es, self.ann, [ ANN_DATA, [ 'Dummy Byte', @@ -367,7 +225,7 @@ class Decoder(srd.Decoder): self._put_command_warning('Invalid header byte.') return - self.put(self.command_start, self.command_end, self.ann, [ + self.putc([ ANN_RBM, [ 'Read Buffer Memory: Length {0}'.format( @@ -379,8 +237,7 @@ class Decoder(srd.Decoder): self._put_data_byte(self.miso[i], i) def _process_wcr(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_WCR, ['Write Control Register', 'WCR']]) + self.putc([ANN_WCR, ['Write Control Register', 'WCR']]) if len(self.mosi) != 2: self._put_command_warning('Invalid command length.') @@ -398,7 +255,7 @@ class Decoder(srd.Decoder): self._put_command_warning('Invalid header byte.') return - self.put(self.command_start, self.command_end, self.ann, [ + self.putc([ ANN_WBM, [ 'Write Buffer Memory: Length {0}'.format( @@ -410,8 +267,7 @@ class Decoder(srd.Decoder): self._put_data_byte(self.mosi[i], i) def _process_bfc(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_BFC, ['Bit Field Clear', 'BFC']]) + self.putc([ANN_BFC, ['Bit Field Clear', 'BFC']]) if len(self.mosi) != 2: self._put_command_warning('Invalid command length.') @@ -427,8 +283,7 @@ class Decoder(srd.Decoder): self.bsel1 = 0 def _process_bfs(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_BFS, ['Bit Field Set', 'BFS']]) + self.putc([ANN_BFS, ['Bit Field Set', 'BFS']]) if len(self.mosi) != 2: self._put_command_warning('Invalid command length.') @@ -444,8 +299,7 @@ class Decoder(srd.Decoder): self.bsel1 = 1 def _process_src(self): - self.put(self.command_start, self.command_end, - self.ann, [ANN_SRC, ['System Reset Command', 'SRC']]) + self.putc([ANN_SRC, ['System Reset Command', 'SRC']]) if len(self.mosi) != 1: self._put_command_warning('Invalid command length.') @@ -462,13 +316,13 @@ class Decoder(srd.Decoder): if new_cs == 0: self.active = True - self.command_start = ss + self.cmd_ss = ss self.mosi = [] self.miso = [] self.ranges = [] elif new_cs == 1: if self.active: - self.command_end = es + self.cmd_es = es self._process_command() elif ptype == 'DATA': mosi, miso = data1, data2