X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fem4100%2Fpd.py;h=4f2751b467abcf83590ab8e68bf58ad448b93c79;hp=e1b931e2ded2c8d5225488f8a15bf43a96029a23;hb=88df2c9a6e125590db12aebb8a4466ebd57978c7;hpb=428e40cb08410595126f245e5379cd3104747937 diff --git a/decoders/em4100/pd.py b/decoders/em4100/pd.py index e1b931e..4f2751b 100644 --- a/decoders/em4100/pd.py +++ b/decoders/em4100/pd.py @@ -5,8 +5,8 @@ ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either data 2 of the License, or -## (at your option) any later data. +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -38,11 +38,11 @@ class Decoder(srd.Decoder): options = ( {'id': 'polarity', 'desc': 'Polarity', 'default': 'active-high', 'values': ('active-low', 'active-high')}, - {'id': 'datarate' , 'desc': 'Data rate', 'default': '64', - 'values': ('64', '32', '16')}, + {'id': 'datarate' , 'desc': 'Data rate', 'default': 64, + 'values': (64, 32, 16)}, # {'id': 'coding', 'desc': 'Bit coding', 'default': 'biphase', # 'values': ('biphase', 'manchester', 'psk')}, - {'id': 'coilfreq', 'desc': 'Coil frequency', 'default': '125000'}, + {'id': 'coilfreq', 'desc': 'Coil frequency', 'default': 125000}, ) annotations = ( ('bit', 'Bit'), @@ -74,12 +74,12 @@ class Decoder(srd.Decoder): self.oldpl = 0 self.oldsamplenum = 0 self.last_bit_pos = 0 - self.first_start = 0 + self.first_ss = 0 self.first_one = 0 self.state = 'HEADER' self.data = 0 self.data_bits = 0 - self.data_start = 0 + self.data_ss = 0 self.data_parity = 0 self.payload_cnt = 0 self.data_col_parity = [0, 0, 0, 0, 0, 0] @@ -91,27 +91,28 @@ class Decoder(srd.Decoder): def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: self.samplerate = value - self.bit_width = (self.samplerate / (int(self.options['coilfreq']))) * int(self.options['datarate']) + self.bit_width = (self.samplerate / self.options['coilfreq']) * self.options['datarate'] self.halfbit_limit = self.bit_width/2 + self.bit_width/4 self.polarity = 0 if self.options['polarity'] == 'active-low' else 1 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) - def add_bit(self, bit, bit_start, bit_stop): + def putbit(self, bit, ss, es): + self.put(ss, es, self.out_ann, [0, [str(bit)]]) if self.state == 'HEADER': if bit == 1: if self.first_one > 0: self.first_one += 1 if self.first_one == 9: - self.put(int(self.first_start), int(bit_stop), self.out_ann, + self.put(self.first_ss, es, self.out_ann, [1, ['Header', 'Head', 'He', 'H']]) self.first_one = 0 self.state = 'PAYLOAD' return if self.first_one == 0: self.first_one = 1 - self.first_start = bit_start + self.first_ss = ss if bit == 0: self.first_one = 0 @@ -120,20 +121,20 @@ class Decoder(srd.Decoder): if self.state == 'PAYLOAD': self.payload_cnt += 1 if self.data_bits == 0: - self.data_start = bit_start + self.data_ss = ss self.data = 0 self.data_parity = 0 self.data_bits += 1 if self.data_bits == 5: s = 'Version/customer' if self.payload_cnt <= 10 else 'Data' c = 2 if self.payload_cnt <= 10 else 3 - self.put(int(self.data_start), int(bit_start), self.out_ann, + self.put(self.data_ss, ss, self.out_ann, [c, [s + ': %X' % self.data, '%X' % self.data]]) s = 'OK' if self.data_parity == bit else 'ERROR' c = 4 if s == 'OK' else 5 if s == 'ERROR': self.all_row_parity_ok = False - self.put(int(bit_start), int(bit_stop), self.out_ann, + self.put(ss, es, self.out_ann, [c, ['Row parity: ' + s, 'RP: ' + s, 'RP', 'R']]) self.tag = (self.tag << 4) | self.data self.data_bits = 0 @@ -149,16 +150,15 @@ class Decoder(srd.Decoder): if self.state == 'TRAILER': self.payload_cnt += 1 if self.data_bits == 0: - self.data_start = bit_start + self.data_ss = ss self.data = 0 self.data_parity = 0 self.data_bits += 1 self.col_parity[self.data_bits] = bit - self.col_parity_pos.append([int(bit_start), int(bit_stop)]) + self.col_parity_pos.append([ss, es]) if self.data_bits == 5: - self.put(int(bit_start), int(bit_stop), self.out_ann, - [8, ['Stop bit', 'SB', 'S']]) + self.put(ss, es, self.out_ann, [8, ['Stop bit', 'SB', 'S']]) for i in range(1, 5): s = 'OK' if self.data_col_parity[i] == \ @@ -172,7 +172,7 @@ class Decoder(srd.Decoder): # Emit an annotation for valid-looking tags. all_col_parity_ok = (self.data_col_parity[1:5] == self.col_parity[1:5]) if all_col_parity_ok and self.all_row_parity_ok: - self.put(int(self.first_start), int(bit_stop), self.out_ann, + self.put(self.first_ss, es, self.out_ann, [9, ['Tag: %010X' % self.tag, 'Tag', 'T']]) self.tag = 0 @@ -186,43 +186,26 @@ class Decoder(srd.Decoder): self.col_parity_pos = [] self.all_row_parity_ok = True - def putbit(self, bit, bit_start, bit_stop): - self.put(int(bit_start), int(bit_stop), self.out_ann, - [0, [str(bit)]]) - self.add_bit(bit, bit_start, bit_stop) - def manchester_decode(self, samplenum, pl, pp, pin): - bit_start = 0 - bit_stop = 0 bit = self.oldpin ^ self.polarity if pl > self.halfbit_limit: - samples = samplenum - self.oldsamplenum - t = samples / self.samplerate - + es = int(samplenum - pl/2) if self.oldpl > self.halfbit_limit: - bit_start = int(self.oldsamplenum - self.oldpl/2) - bit_stop = int(samplenum - pl/2) - self.putbit(bit, bit_start, bit_stop) - if self.oldpl <= self.halfbit_limit: - bit_start = int(self.oldsamplenum - self.oldpl) - bit_stop = int(samplenum - pl/2) - self.putbit(bit, bit_start, bit_stop) + ss = int(self.oldsamplenum - self.oldpl/2) + else: + ss = int(self.oldsamplenum - self.oldpl) + self.putbit(bit, ss, es) self.last_bit_pos = int(samplenum - pl/2) - - if pl < self.halfbit_limit: - samples = samplenum - self.oldsamplenum - t = samples / self.samplerate - + else: + es = int(samplenum) if self.oldpl > self.halfbit_limit: - bit_start = self.oldsamplenum - self.oldpl/2 - bit_stop = int(samplenum) - self.putbit(bit, bit_start, bit_stop) + ss = int(self.oldsamplenum - self.oldpl/2) + self.putbit(bit, ss, es) self.last_bit_pos = int(samplenum) - if self.oldpl <= self.halfbit_limit: + else: if self.last_bit_pos <= self.oldsamplenum - self.oldpl: - bit_start = self.oldsamplenum - self.oldpl - bit_stop = int(samplenum) - self.putbit(bit, bit_start, bit_stop) + ss = int(self.oldsamplenum - self.oldpl) + self.putbit(bit, ss, es) self.last_bit_pos = int(samplenum) def decode(self, ss, es, data): @@ -247,9 +230,7 @@ class Decoder(srd.Decoder): if self.oldpin != pin: pl = samplenum - self.oldsamplenum pp = pin - self.manchester_decode(samplenum, pl, pp, pin) - self.oldpl = pl self.oldpp = pp self.oldsamplenum = samplenum