X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fdsi%2Fpd.py;h=7ce95179f9aa7f9a254793b37229ecfcd235253f;hp=dc19ba2636747bcbd90938ee8564c1526238b442;hb=6cbba91f23b9f9ace75b4722c9c0776b9211008d;hpb=23a8a38357ed6917d2471f46f65b158379ad564e

diff --git a/decoders/dsi/pd.py b/decoders/dsi/pd.py
index dc19ba2..7ce9517 100644
--- a/decoders/dsi/pd.py
+++ b/decoders/dsi/pd.py
@@ -23,14 +23,15 @@ class SamplerateError(Exception):
     pass
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'dsi'
     name = 'DSI'
-    longname = 'Digital Serial Interface Lighting'
-    desc = 'DSI lighting control protocol.'
+    longname = 'Digital Serial Interface'
+    desc = 'Digital Serial Interface (DSI) lighting protocol.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['dsi']
+    outputs = []
+    tags = ['Embedded/industrial', 'Lighting']
     channels = (
         {'id': 'dsi', 'name': 'DSI', 'desc': 'DSI data line'},
     )
@@ -40,27 +41,28 @@ class Decoder(srd.Decoder):
     )
     annotations = (
         ('bit', 'Bit'),
-        ('startbit', 'Startbit'),
-        ('Level', 'Dimmer level'),
+        ('startbit', 'Start bit'),
+        ('level', 'Dimmer level'),
         ('raw', 'Raw data'),
     )
     annotation_rows = (
         ('bits', 'Bits', (0,)),
-        ('raw', 'Raw Data',(3,)),
-        ('fields', 'Fields', (1, 2,)),
+        ('raw', 'Raw data', (3,)),
+        ('fields', 'Fields', (1, 2)),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.samplenum = None
         self.edges, self.bits, self.ss_es_bits = [], [], []
         self.state = 'IDLE'
-        self.nextSamplePoint = None
-        self.nextSample = None
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
-        self.old_ir = 1 if self.options['polarity'] == 'active-low' else 0
+        self.old_dsi = 1 if self.options['polarity'] == 'active-low' else 0
 
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
@@ -105,53 +107,46 @@ class Decoder(srd.Decoder):
         self.edges, self.bits, self.ss_es_bits = [], [], []
         self.state = 'IDLE'
 
-    def decode(self, ss, es, data):
+    def decode(self):
         if not self.samplerate:
             raise SamplerateError('Cannot decode without samplerate.')
-        bit = 0;
-        for (self.samplenum, pins) in data:
-            self.ir = pins[0]
-            # data.itercnt += 1
+        bit = 0
+        while True:
+            (self.dsi,) = self.wait()
             if self.options['polarity'] == 'active-high':
-                self.ir ^= 1 # Invert.
+                self.dsi ^= 1 # Invert.
 
             # State machine.
             if self.state == 'IDLE':
                 # Wait for any edge (rising or falling).
-                if self.old_ir == self.ir:
+                if self.old_dsi == self.dsi:
                     continue
                 # Add in the first half of the start bit.
                 self.edges.append(self.samplenum - int(self.halfbit))
                 self.edges.append(self.samplenum)
                 # Start bit is 0->1.
-                self.phase0 = self.ir ^ 1
+                self.phase0 = self.dsi ^ 1
                 self.state = 'PHASE1'
-                self.old_ir = self.ir
+                self.old_dsi = self.dsi
                 # Get the next sample point.
-                # self.nextSamplePoint = self.samplenum + int(self.halfbit / 2)
-                self.old_ir = self.ir
-                # bit = self.ir
+                self.old_dsi = self.dsi
                 continue
 
-            # if(self.samplenum == self.nextSamplePoint):
-            #    bit = self.ir
-            #    continue
-
-            if self.old_ir != self.ir:
+            if self.old_dsi != self.dsi:
                 self.edges.append(self.samplenum)
             elif self.samplenum == (self.edges[-1] + int(self.halfbit * 1.5)):
                 self.edges.append(self.samplenum - int(self.halfbit * 0.5))
             else:
                 continue
 
-            bit = self.old_ir
+            bit = self.old_dsi
             if self.state == 'PHASE0':
                 self.phase0 = bit
                 self.state = 'PHASE1'
             elif self.state == 'PHASE1':
-                if (bit == 1) and (self.phase0 == 1): # Stop bit
+                if (bit == 1) and (self.phase0 == 1): # Stop bit.
                     if len(self.bits) == 17 or len(self.bits) == 9:
-                        # Forward or Backward
+                        # Forward or Backward.
                         self.handle_bits(len(self.bits))
                     self.reset_decoder_state() # Reset upon errors.
                     continue
@@ -159,6 +154,4 @@ class Decoder(srd.Decoder):
                     self.bits.append([self.edges[-3], bit])
                     self.state = 'PHASE0'
 
-            # self.nextSamplePoint = self.edges[-1] + int(self.halfbit / 2)
-
-            self.old_ir = self.ir
+            self.old_dsi = self.dsi