X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fds1307%2Fpd.py;h=920f12586eb42170aa2f057d38f3dee13a54ca61;hp=556d5930c30327c9c43f02756049ff63e28f6138;hb=09d8bda971308222cc891bbc7ed9d0b839e1d17b;hpb=2787cf2abc0187679e87d3735ca3e64c2a1a91c8

diff --git a/decoders/ds1307/pd.py b/decoders/ds1307/pd.py
index 556d593..920f125 100644
--- a/decoders/ds1307/pd.py
+++ b/decoders/ds1307/pd.py
@@ -47,8 +47,8 @@ rates = {
 DS1307_I2C_ADDRESS = 0x68
 
 def regs_and_bits():
-    l = [('reg-' + r.lower(), r + ' register') for r in regs]
-    l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits]
+    l = [('reg_' + r.lower(), r + ' register') for r in regs]
+    l += [('bit_' + re.sub('\/| ', '_', b).lower(), b + ' bit') for b in bits]
     return tuple(l)
 
 class Decoder(srd.Decoder):
@@ -59,19 +59,19 @@ class Decoder(srd.Decoder):
     desc = 'Dallas DS1307 realtime clock module protocol.'
     license = 'gplv2+'
     inputs = ['i2c']
-    outputs = ['ds1307']
+    outputs = []
     tags = ['Clock/timing', 'IC']
     annotations =  regs_and_bits() + (
-        ('read-datetime', 'Read date/time'),
-        ('write-datetime', 'Write date/time'),
-        ('reg-read', 'Register read'),
-        ('reg-write', 'Register write'),
-        ('warnings', 'Warnings'),
+        ('read_date_time', 'Read date/time'),
+        ('write_date_time', 'Write date/time'),
+        ('reg_read', 'Register read'),
+        ('reg_write', 'Register write'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('bits', 'Bits', tuple(range(9, 24))),
         ('regs', 'Registers', tuple(range(9))),
-        ('date-time', 'Date/time', (24, 25, 26, 27)),
+        ('date_time', 'Date/time', (24, 25, 26, 27)),
         ('warnings', 'Warnings', (28,)),
     )