X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fcan%2Fpd.py;h=e2b55fa3c62f89fd3a2a3e6f9403710b1a37084e;hp=45b7a18400e0b7eb7da8abae3d9a576cc4138407;hb=84c1c0b52820af2418186ac3ecf93a5c6373a22e;hpb=50bd5d259677faf87bb3408e111d0e833d7ba9b4 diff --git a/decoders/can/pd.py b/decoders/can/pd.py index 45b7a18..e2b55fa 100644 --- a/decoders/can/pd.py +++ b/decoders/can/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2012 Uwe Hermann +## Copyright (C) 2012-2013 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,8 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# CAN protocol decoder - import sigrokdecode as srd class Decoder(srd.Decoder): @@ -35,28 +33,60 @@ class Decoder(srd.Decoder): {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, ] optional_probes = [] - options = { - 'bitrate': ['Bitrate', 1000000], # 1Mbit/s - 'sample_point': ['Sample point', 70], # 70% - } + options = ( + {'id': 'bitrate', 'desc': 'Bitrate', 'default': 1000000}, # 1Mbit/s + {'id': 'sample_point', 'desc': 'Sample point', 'default': 70}, # 70% + ) annotations = [ - ['Text', 'Human-readable text'], - ['Warnings', 'Human-readable warnings'], + ['data', 'CAN payload data'], + ['sof', 'Start of frame'], + ['eof', 'End of frame'], + ['id', 'Identifier'], + ['ext-id', 'Extended identifier'], + ['full-id', 'Full identifier'], + ['ide', 'Identifier extension bit'], + ['reserved-bit', 'Reserved bit 0 and 1'], + ['rtr', 'Remote transmission request'], + ['srr', 'Substitute remote request'], + ['dlc', 'Data length count'], + ['crc-sequence', 'CRC sequence'], + ['crc-delimiter', 'CRC delimiter'], + ['ack-slot', 'ACK slot'], + ['ack-delimiter', 'ACK delimiter'], + ['stuff-bit', 'Stuff bit'], + ['warnings', 'Human-readable warnings'], ] def __init__(self, **kwargs): + self.samplerate = None self.reset_variables() - def start(self, metadata): - # self.out_proto = self.add(srd.OUTPUT_PROTO, 'can') - self.out_ann = self.add(srd.OUTPUT_ANN, 'can') + def start(self): + # self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) + + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + self.bit_width = float(self.samplerate) / float(self.options['bitrate']) + self.bitpos = (self.bit_width / 100.0) * self.options['sample_point'] + + # Generic helper for CAN bit annotations. + def putg(self, ss, es, data): + left, right = int(self.bitpos), int(self.bit_width - self.bitpos) + self.put(ss - left, es + right, self.out_ann, data) + + # Single-CAN-bit annotation using the current samplenum. + def putx(self, data): + self.putg(self.samplenum, self.samplenum, data) - self.samplerate = metadata['samplerate'] - self.bit_width = float(self.samplerate) / float(self.options['bitrate']) - self.bitpos = (self.bit_width / 100.0) * self.options['sample_point'] + # Single-CAN-bit annotation using the samplenum of CAN bit 12. + def put12(self, data): + self.putg(self.ss_bit12, self.ss_bit12, data) - def report(self): - pass + # Multi-CAN-bit annotation from self.ss_block to current samplenum. + def putb(self, data): + self.putg(self.ss_block, self.samplenum, data) def reset_variables(self): self.state = 'IDLE' @@ -65,6 +95,9 @@ class Decoder(srd.Decoder): self.bits = [] # Only actual CAN frame bits (no stuff bits) self.curbit = 0 # Current bit of CAN frame (bit 0 == SOF) self.last_databit = 999 # Positive value that bitnum+x will never match + self.ss_block = None + self.ss_bit12 = None + self.ss_databytebits = [] # Return True if we reached the desired bit position, False otherwise. def reached_bit(self, bitnum): @@ -81,7 +114,8 @@ class Decoder(srd.Decoder): return False # Stuff bit. Keep it in self.rawbits, but drop it from self.bits. - self.put(0, 0, self.out_ann, [0, ['Stuff bit: %d' % self.rawbits[-1]]]) + self.putx([15, ['Stuff bit: %d' % self.rawbits[-1], + 'SB: %d' % self.rawbits[-1], 'SB']]) self.bits.pop() # Drop last bit. return True @@ -99,32 +133,42 @@ class Decoder(srd.Decoder): # Returns True if the frame ended (EOF), False otherwise. def decode_frame_end(self, can_rx, bitnum): + # Remember start of CRC sequence (see below). + if bitnum == (self.last_databit + 1): + self.ss_block = self.samplenum + # CRC sequence (15 bits) - if bitnum == (self.last_databit + 15): + elif bitnum == (self.last_databit + 15): x = self.last_databit + 1 crc_bits = self.bits[x:x + 15 + 1] self.crc = int(''.join(str(d) for d in crc_bits), 2) - self.put(0, 0, self.out_ann, [0, ['CRC: 0x%04x' % self.crc]]) - + self.putb([11, ['CRC sequence: 0x%04x' % self.crc, + 'CRC: 0x%04x' % self.crc, 'CRC']]) if not self.is_valid_crc(crc_bits): - self.put(0, 0, self.out_ann, [0, ['CRC is invalid']]) + self.putb([16, ['CRC is invalid']]) # CRC delimiter bit (recessive) elif bitnum == (self.last_databit + 16): - self.put(0, 0, self.out_ann, [0, ['CRC delimiter: %d' % can_rx]]) + self.putx([12, ['CRC delimiter: %d' % can_rx, + 'CRC d: %d' % can_rx, 'CRC d']]) # ACK slot bit (dominant: ACK, recessive: NACK) elif bitnum == (self.last_databit + 17): ack = 'ACK' if can_rx == 0 else 'NACK' - self.put(0, 0, self.out_ann, [0, ['ACK slot: %s' % ack]]) + self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) # ACK delimiter bit (recessive) elif bitnum == (self.last_databit + 18): - self.put(0, 0, self.out_ann, [0, ['ACK delimiter: %d' % can_rx]]) + self.putx([14, ['ACK delimiter: %d' % can_rx, + 'ACK d: %d' % can_rx, 'ACK d']]) + + # Remember start of EOF (see below). + elif bitnum == (self.last_databit + 19): + self.ss_block = self.samplenum # End of frame (EOF), 7 recessive bits elif bitnum == (self.last_databit + 25): - self.put(0, 0, self.out_ann, [0, ['End of frame', 'EOF']]) + self.putb([2, ['End of frame', 'EOF', 'E']]) self.reset_variables() return True @@ -136,28 +180,43 @@ class Decoder(srd.Decoder): # Bit 14: RB0 (reserved bit) # Has to be sent dominant, but receivers should accept recessive too. if bitnum == 14: - self.put(0, 0, self.out_ann, [0, ['RB0: %d' % can_rx]]) + self.putx([7, ['Reserved bit 0: %d' % can_rx, + 'RB0: %d' % can_rx, 'RB0']]) # Bit 12: Remote transmission request (RTR) bit # Data frame: dominant, remote frame: recessive # Remote frames do not contain a data field. rtr = 'remote' if self.bits[12] == 1 else 'data' - self.put(0, 0, self.out_ann, [0, ['RTR: %s frame' % rtr]]) + self.put12([8, ['Remote transmission request: %s frame' % rtr, + 'RTR: %s frame' % rtr, 'RTR']]) + + # Remember start of DLC (see below). + elif bitnum == 15: + self.ss_block = self.samplenum # Bits 15-18: Data length code (DLC), in number of bytes (0-8). elif bitnum == 18: self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2) - self.put(0, 0, self.out_ann, [0, ['DLC: %d' % self.dlc]]) + self.putb([10, ['Data length code: %d' % self.dlc, + 'DLC: %d' % self.dlc, 'DLC']]) self.last_databit = 18 + (self.dlc * 8) + # Remember all databyte bits, except the very last one. + elif bitnum in range(19, self.last_databit): + self.ss_databytebits.append(self.samplenum) + # Bits 19-X: Data field (0-8 bytes, depending on DLC) # The bits within a data byte are transferred MSB-first. elif bitnum == self.last_databit: + self.ss_databytebits.append(self.samplenum) # Last databyte bit. for i in range(self.dlc): x = 18 + (8 * i) + 1 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) - self.put(0, 0, self.out_ann, - [0, ['Data byte %d: 0x%02x' % (i, b)]]) + ss = self.ss_databytebits[i * 8] + es = self.ss_databytebits[((i + 1) * 8) - 1] + self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), + 'DB %d: 0x%02x' % (i, b), 'DB']]) + self.ss_databytebits = [] elif bitnum > self.last_databit: return self.decode_frame_end(can_rx, bitnum) @@ -167,48 +226,71 @@ class Decoder(srd.Decoder): # Returns True if the frame ended (EOF), False otherwise. def decode_extended_frame(self, can_rx, bitnum): + # Remember start of EID (see below). + if bitnum == 14: + self.ss_block = self.samplenum + # Bits 14-31: Extended identifier (EID[17..0]) - if bitnum == 31: + elif bitnum == 31: self.eid = int(''.join(str(d) for d in self.bits[14:]), 2) - self.put(0, 0, self.out_ann, - [0, ['Extended ID: %d (0x%x)' % (self.eid, self.eid)]]) + s = '%d (0x%x)' % (self.eid, self.eid) + self.putb([4, ['Extended Identifier: %s' % s, + 'Extended ID: %s' % s, 'Extended ID', 'EID']]) self.fullid = self.id << 18 | self.eid - self.put(0, 0, self.out_ann, - [0, ['Full ID: %d (0x%x)' % (self.fullid, self.fullid)]]) + s = '%d (0x%x)' % (self.fullid, self.fullid) + self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s, + 'Full ID', 'FID']]) # Bit 12: Substitute remote request (SRR) bit - self.put(0, 0, self.out_ann, [0, ['SRR: %d' % self.bits[12]]]) + self.put12([9, ['Substitute remote request: %d' % self.bits[12], + 'SRR: %d' % self.bits[12], 'SRR']]) # Bit 32: Remote transmission request (RTR) bit # Data frame: dominant, remote frame: recessive # Remote frames do not contain a data field. if bitnum == 32: rtr = 'remote' if can_rx == 1 else 'data' - self.put(0, 0, self.out_ann, [0, ['RTR: %s frame' % rtr]]) + self.putx([8, ['Remote transmission request: %s frame' % rtr, + 'RTR: %s frame' % rtr, 'RTR']]) # Bit 33: RB1 (reserved bit) elif bitnum == 33: - self.put(0, 0, self.out_ann, [0, ['RB1: %d' % can_rx]]) + self.putx([7, ['Reserved bit 1: %d' % can_rx, + 'RB1: %d' % can_rx, 'RB1']]) # Bit 34: RB0 (reserved bit) elif bitnum == 34: - self.put(0, 0, self.out_ann, [0, ['RB0: %d' % can_rx]]) + self.putx([7, ['Reserved bit 0: %d' % can_rx, + 'RB0: %d' % can_rx, 'RB0']]) + + # Remember start of DLC (see below). + elif bitnum == 35: + self.ss_block = self.samplenum # Bits 35-38: Data length code (DLC), in number of bytes (0-8). elif bitnum == 38: self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2) - self.put(0, 0, self.out_ann, [0, ['DLC: %d' % self.dlc]]) + self.putb([10, ['Data length code: %d' % self.dlc, + 'DLC: %d' % self.dlc, 'DLC']]) self.last_databit = 38 + (self.dlc * 8) + # Remember all databyte bits, except the very last one. + elif bitnum in range(39, self.last_databit): + self.ss_databytebits.append(self.samplenum) + # Bits 39-X: Data field (0-8 bytes, depending on DLC) # The bits within a data byte are transferred MSB-first. elif bitnum == self.last_databit: + self.ss_databytebits.append(self.samplenum) # Last databyte bit. for i in range(self.dlc): x = 38 + (8 * i) + 1 b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) - self.put(0, 0, self.out_ann, - [0, ['Data byte %d: 0x%02x' % (i, b)]]) + ss = self.ss_databytebits[i * 8] + es = self.ss_databytebits[((i + 1) * 8) - 1] + self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b), + 'DB %d: 0x%02x' % (i, b), 'DB']]) + self.ss_databytebits = [] elif bitnum > self.last_databit: return self.decode_frame_end(can_rx, bitnum) @@ -223,8 +305,8 @@ class Decoder(srd.Decoder): bitnum = len(self.bits) - 1 # For debugging. - # self.put(0, 0, self.out_ann, [0, ['Bit %d (CAN bit %d): %d' % \ - # (self.curbit, bitnum, can_rx)]]) + # self.putx([0, ['Bit %d (CAN bit %d): %d' % \ + # (self.curbit, bitnum, can_rx)]]) # If this is a stuff bit, remove it from self.bits and ignore it. if self.is_stuff_bit(): @@ -234,28 +316,32 @@ class Decoder(srd.Decoder): # Bit 0: Start of frame (SOF) bit if bitnum == 0: if can_rx == 0: - self.put(0, 0, self.out_ann, [0, ['Start of frame', 'SOF']]) + self.putx([1, ['Start of frame', 'SOF', 'S']]) else: - self.put(0, 0, self.out_ann, - [1, ['Start of frame (SOF) must be a dominant bit']]) + self.putx([16, ['Start of frame (SOF) must be a dominant bit']]) + + # Remember start of ID (see below). + elif bitnum == 1: + self.ss_block = self.samplenum # Bits 1-11: Identifier (ID[10..0]) # The bits ID[10..4] must NOT be all recessive. elif bitnum == 11: self.id = int(''.join(str(d) for d in self.bits[1:]), 2) - self.put(0, 0, self.out_ann, - [0, ['ID: %d (0x%x)' % (self.id, self.id)]]) + s = '%d (0x%x)' % (self.id, self.id), + self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']]) # RTR or SRR bit, depending on frame type (gets handled later). elif bitnum == 12: - # self.put(0, 0, self.out_ann, [0, ['RTR/SRR: %d' % can_rx]]) - pass + # self.putx([0, ['RTR/SRR: %d' % can_rx]]) # Debug only. + self.ss_bit12 = self.samplenum # Bit 13: Identifier extension (IDE) bit # Standard frame: dominant, extended frame: recessive elif bitnum == 13: ide = self.frame_type = 'standard' if can_rx == 0 else 'extended' - self.put(0, 0, self.out_ann, [0, ['IDE: %s frame' % ide]]) + self.putx([6, ['Identifier extension bit: %s frame' % ide, + 'IDE: %s frame' % ide, 'IDE']]) # Bits 14-X: Frame-type dependent, passed to the resp. handlers. elif bitnum >= 14: @@ -274,6 +360,8 @@ class Decoder(srd.Decoder): self.curbit += 1 def decode(self, ss, es, data): + if self.samplerate is None: + raise Exception("Cannot decode without samplerate.") for (self.samplenum, pins) in data: (can_rx,) = pins @@ -284,7 +372,6 @@ class Decoder(srd.Decoder): if can_rx == 1: continue self.sof = self.samplenum - # self.put(self.sof, self.sof, self.out_ann, [0, ['SOF']]) self.state = 'GET BITS' elif self.state == 'GET BITS': # Wait until we're in the correct bit/sampling position.