X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fcan%2Fpd.py;h=0b001278a1905e9f27042d168e9a43fc2026645a;hp=056736b85de83560b13d10283ea1ca892e393fe2;hb=ad37302991cd5690bd1eb4db4abcad206fae42ec;hpb=10aeb8ea8b183394cebc0033f048f49f4262b57d diff --git a/decoders/can/pd.py b/decoders/can/pd.py index 056736b..0b00127 100644 --- a/decoders/can/pd.py +++ b/decoders/can/pd.py @@ -2,6 +2,7 @@ ## This file is part of the libsigrokdecode project. ## ## Copyright (C) 2012-2013 Uwe Hermann +## Copyright (C) 2019 Stephan Thiele ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -22,6 +23,9 @@ import sigrokdecode as srd class SamplerateError(Exception): pass +def dlc2len(dlc): + return [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64][dlc] + class Decoder(srd.Decoder): api_version = 3 id = 'can' @@ -30,12 +34,14 @@ class Decoder(srd.Decoder): desc = 'Field bus protocol for distributed realtime control.' license = 'gplv2+' inputs = ['logic'] - outputs = ['can'] + outputs = [] + tags = ['Automotive'] channels = ( {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'}, ) options = ( - {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000}, + {'id': 'nominal_bitrate', 'desc': 'Nominal bitrate (bits/s)', 'default': 1000000}, + {'id': 'fast_bitrate', 'desc': 'Fast bitrate (bits/s)', 'default': 2000000}, {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0}, ) annotations = ( @@ -77,7 +83,7 @@ class Decoder(srd.Decoder): def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: self.samplerate = value - self.bit_width = float(self.samplerate) / float(self.options['bitrate']) + self.bit_width = float(self.samplerate) / float(self.options['nominal_bitrate']) self.sample_point = (self.bit_width / 100.0) * self.options['sample_point'] # Generic helper for CAN bit annotations. @@ -93,6 +99,10 @@ class Decoder(srd.Decoder): def put12(self, data): self.putg(self.ss_bit12, self.ss_bit12, data) + # Single-CAN-bit annotation using the samplenum of CAN bit 32. + def put32(self, data): + self.putg(self.ss_bit32, self.ss_bit32, data) + # Multi-CAN-bit annotation from self.ss_block to current samplenum. def putb(self, data): self.putg(self.ss_block, self.samplenum, data) @@ -106,7 +116,10 @@ class Decoder(srd.Decoder): self.last_databit = 999 # Positive value that bitnum+x will never match self.ss_block = None self.ss_bit12 = None + self.ss_bit32 = None self.ss_databytebits = [] + self.fd = False + self.rtr = None # Poor man's clock synchronization. Use signal edges which change to # dominant state in rather simple ways. This naive approach is neither @@ -132,7 +145,7 @@ class Decoder(srd.Decoder): # CAN uses NRZ encoding and bit stuffing. # After 5 identical bits, a stuff bit of opposite value is added. # But not in the CRC delimiter, ACK, and end of frame fields. - if len(self.bits) > self.last_databit + 16: + if len(self.bits) > self.last_databit + 17: return False last_6_bits = self.rawbits[-6:] if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]): @@ -159,42 +172,57 @@ class Decoder(srd.Decoder): # Remember start of CRC sequence (see below). if bitnum == (self.last_databit + 1): self.ss_block = self.samplenum + if self.fd: + if dlc2len(self.dlc) < 16: + self.crc_len = 27 # 17 + SBC + stuff bits + else: + self.crc_len = 32 # 21 + SBC + stuff bits + else: + self.crc_len = 15 + + # CRC sequence (15 bits, 17 bits or 21 bits) + elif bitnum == (self.last_databit + self.crc_len): + if self.fd: + if dlc2len(self.dlc) < 16: + crc_type = "CRC-17" + else: + crc_type = "CRC-21" + else: + crc_type = "CRC" # TODO: CRC-15 (will break existing tests) - # CRC sequence (15 bits) - elif bitnum == (self.last_databit + 15): x = self.last_databit + 1 - crc_bits = self.bits[x:x + 15 + 1] + crc_bits = self.bits[x:x + self.crc_len + 1] self.crc = int(''.join(str(d) for d in crc_bits), 2) - self.putb([11, ['CRC sequence: 0x%04x' % self.crc, - 'CRC: 0x%04x' % self.crc, 'CRC']]) + self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc), + '%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]]) if not self.is_valid_crc(crc_bits): self.putb([16, ['CRC is invalid']]) # CRC delimiter bit (recessive) - elif bitnum == (self.last_databit + 16): + elif bitnum == (self.last_databit + self.crc_len + 1): self.putx([12, ['CRC delimiter: %d' % can_rx, 'CRC d: %d' % can_rx, 'CRC d']]) if can_rx != 1: self.putx([16, ['CRC delimiter must be a recessive bit']]) # ACK slot bit (dominant: ACK, recessive: NACK) - elif bitnum == (self.last_databit + 17): + elif bitnum == (self.last_databit + self.crc_len + 2): ack = 'ACK' if can_rx == 0 else 'NACK' self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']]) # ACK delimiter bit (recessive) - elif bitnum == (self.last_databit + 18): + elif bitnum == (self.last_databit + self.crc_len + 3): self.putx([14, ['ACK delimiter: %d' % can_rx, 'ACK d: %d' % can_rx, 'ACK d']]) if can_rx != 1: self.putx([16, ['ACK delimiter must be a recessive bit']]) # Remember start of EOF (see below). - elif bitnum == (self.last_databit + 19): + elif bitnum == (self.last_databit + self.crc_len + 4): self.ss_block = self.samplenum # End of frame (EOF), 7 recessive bits - elif bitnum == (self.last_databit + 25): + elif bitnum == (self.last_databit + self.crc_len + 10): self.putb([2, ['End of frame', 'EOF', 'E']]) if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]: self.putb([16, ['End of frame (EOF) must be 7 recessive bits']]) @@ -206,42 +234,63 @@ class Decoder(srd.Decoder): # Returns True if the frame ended (EOF), False otherwise. def decode_standard_frame(self, can_rx, bitnum): - # Bit 14: RB0 (reserved bit) - # Has to be sent dominant, but receivers should accept recessive too. + # Bit 14: FDF (Flexible data format) + # Has to be sent dominant when FD frame, has to be sent recessive + # when classic CAN frame. if bitnum == 14: - self.putx([7, ['Reserved bit 0: %d' % can_rx, - 'RB0: %d' % can_rx, 'RB0']]) + self.fd = True if can_rx else False + if self.fd: + self.putx([7, ['Flexible data format: %d' % can_rx, + 'FDF: %d' % can_rx, 'FDF']]) + else: + self.putx([7, ['Reserved bit 0: %d' % can_rx, + 'RB0: %d' % can_rx, 'RB0']]) + + if self.fd: + # Bit 12: Substitute remote request (SRR) bit + self.put12([8, ['Substitute remote request', 'SRR']]) + self.dlc_start = 18 + else: + # Bit 12: Remote transmission request (RTR) bit + # Data frame: dominant, remote frame: recessive + # Remote frames do not contain a data field. + rtr = 'remote' if self.bits[12] == 1 else 'data' + self.put12([8, ['Remote transmission request: %s frame' % rtr, + 'RTR: %s frame' % rtr, 'RTR']]) + self.dlc_start = 15 + + if bitnum == 15 and self.fd: + self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']]) - # Bit 12: Remote transmission request (RTR) bit - # Data frame: dominant, remote frame: recessive - # Remote frames do not contain a data field. - rtr = 'remote' if self.bits[12] == 1 else 'data' - self.put12([8, ['Remote transmission request: %s frame' % rtr, - 'RTR: %s frame' % rtr, 'RTR']]) + if bitnum == 16 and self.fd: + self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']]) + + if bitnum == 17 and self.fd: + self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']]) # Remember start of DLC (see below). - elif bitnum == 15: + elif bitnum == self.dlc_start: self.ss_block = self.samplenum # Bits 15-18: Data length code (DLC), in number of bytes (0-8). - elif bitnum == 18: - self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2) + elif bitnum == self.dlc_start + 3: + self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2) self.putb([10, ['Data length code: %d' % self.dlc, 'DLC: %d' % self.dlc, 'DLC']]) - self.last_databit = 18 + (self.dlc * 8) - if self.dlc > 8: + self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8) + if self.dlc > 8 and not self.fd: self.putb([16, ['Data length code (DLC) > 8 is not allowed']]) # Remember all databyte bits, except the very last one. - elif bitnum in range(19, self.last_databit): + elif bitnum in range(self.dlc_start + 4, self.last_databit): self.ss_databytebits.append(self.samplenum) # Bits 19-X: Data field (0-8 bytes, depending on DLC) # The bits within a data byte are transferred MSB-first. elif bitnum == self.last_databit: self.ss_databytebits.append(self.samplenum) # Last databyte bit. - for i in range(self.dlc): - x = 18 + (8 * i) + 1 + for i in range(dlc2len(self.dlc)): + x = self.dlc_start + 4 + (8 * i) b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) ss = self.ss_databytebits[i * 8] es = self.ss_databytebits[((i + 1) * 8) - 1] @@ -260,6 +309,8 @@ class Decoder(srd.Decoder): # Remember start of EID (see below). if bitnum == 14: self.ss_block = self.samplenum + self.fd = False + self.dlc_start = 35 # Bits 14-31: Extended identifier (EID[17..0]) elif bitnum == 31: @@ -280,42 +331,64 @@ class Decoder(srd.Decoder): # Bit 32: Remote transmission request (RTR) bit # Data frame: dominant, remote frame: recessive # Remote frames do not contain a data field. + + # Remember start of RTR (see below). if bitnum == 32: - rtr = 'remote' if can_rx == 1 else 'data' - self.putx([8, ['Remote transmission request: %s frame' % rtr, - 'RTR: %s frame' % rtr, 'RTR']]) + self.ss_bit32 = self.samplenum + self.rtr = can_rx + + if not self.fd: + rtr = 'remote' if can_rx == 1 else 'data' + self.putx([8, ['Remote transmission request: %s frame' % rtr, + 'RTR: %s frame' % rtr, 'RTR']]) # Bit 33: RB1 (reserved bit) elif bitnum == 33: - self.putx([7, ['Reserved bit 1: %d' % can_rx, - 'RB1: %d' % can_rx, 'RB1']]) + self.fd = True if can_rx else False + if self.fd: + self.dlc_start = 37 + self.putx([7, ['Flexible data format: %d' % can_rx, + 'FDF: %d' % can_rx, 'FDF']]) + self.put32([7, ['Reserved bit 1: %d' % self.rtr, + 'RB1: %d' % self.rtr, 'RB1']]) + else: + self.putx([7, ['Reserved bit 1: %d' % can_rx, + 'RB1: %d' % can_rx, 'RB1']]) # Bit 34: RB0 (reserved bit) elif bitnum == 34: self.putx([7, ['Reserved bit 0: %d' % can_rx, 'RB0: %d' % can_rx, 'RB0']]) + elif bitnum == 35 and self.fd: + self.putx([7, ['Bit rate switch: %d' % can_rx, + 'BRS: %d' % can_rx, 'BRS']]) + + elif bitnum == 36 and self.fd: + self.putx([7, ['Error state indicator: %d' % can_rx, + 'ESI: %d' % can_rx, 'ESI']]) + # Remember start of DLC (see below). - elif bitnum == 35: + elif bitnum == self.dlc_start: self.ss_block = self.samplenum # Bits 35-38: Data length code (DLC), in number of bytes (0-8). - elif bitnum == 38: - self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2) + elif bitnum == self.dlc_start + 3: + self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2) self.putb([10, ['Data length code: %d' % self.dlc, 'DLC: %d' % self.dlc, 'DLC']]) - self.last_databit = 38 + (self.dlc * 8) + self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8) # Remember all databyte bits, except the very last one. - elif bitnum in range(39, self.last_databit): + elif bitnum in range(self.dlc_start + 4, self.last_databit): self.ss_databytebits.append(self.samplenum) # Bits 39-X: Data field (0-8 bytes, depending on DLC) # The bits within a data byte are transferred MSB-first. elif bitnum == self.last_databit: self.ss_databytebits.append(self.samplenum) # Last databyte bit. - for i in range(self.dlc): - x = 38 + (8 * i) + 1 + for i in range(dlc2len(self.dlc)): + x = self.dlc_start + 4 + (8 * i) b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2) ss = self.ss_databytebits[i * 8] es = self.ss_databytebits[((i + 1) * 8) - 1]