X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fam230x%2Fpd.py;h=3d36cbb510dc38d92dbf7616ce1195b64ca7e9aa;hp=483dc9be9792497b471c11c46cefa5fc21445b0d;hb=d6d8a8a440ea2a81e6ddde33d16bc84d01cdb432;hpb=92b7b49f6964f57a7d6fc4473645c993cfa4ba52 diff --git a/decoders/am230x/pd.py b/decoders/am230x/pd.py index 483dc9b..3d36cbb 100644 --- a/decoders/am230x/pd.py +++ b/decoders/am230x/pd.py @@ -14,8 +14,7 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd @@ -35,7 +34,7 @@ class SamplerateError(Exception): pass class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'am230x' name = 'AM230x/DHTxx/RHTxx' longname = 'Aosong AM230x/DHTxx/RHTxx' @@ -43,6 +42,7 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['am230x'] + tags = ['IC', 'Sensor'] channels = ( {'id': 'sda', 'name': 'SDA', 'desc': 'Single wire serial data line'}, ) @@ -75,9 +75,8 @@ class Decoder(srd.Decoder): def putv(self, data): self.put(self.bytepos[-2], self.samplenum, self.out_ann, data) - def reset(self): + def reset_variables(self): self.state = 'WAIT FOR START LOW' - self.samplenum = 0 self.fall = 0 self.rise = 0 self.bits = [] @@ -124,9 +123,12 @@ class Decoder(srd.Decoder): return checksum % 256 def __init__(self): - self.samplerate = None self.reset() + def reset(self): + self.samplerate = None + self.reset_variables() + def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) @@ -164,72 +166,64 @@ class Decoder(srd.Decoder): self.state = 'WAIT FOR END' self.bytepos.append(self.samplenum) - def decode(self, ss, es, data): + def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') - for (self.samplenum, (sda,)) in data: + while True: # State machine. if self.state == 'WAIT FOR START LOW': - if sda != 0: - continue + self.wait({0: 'f'}) self.fall = self.samplenum self.state = 'WAIT FOR START HIGH' elif self.state == 'WAIT FOR START HIGH': - if sda != 1: - continue + self.wait({0: 'r'}) if self.is_valid('START LOW'): self.rise = self.samplenum self.state = 'WAIT FOR RESPONSE LOW' else: - self.reset() + self.reset_variables() elif self.state == 'WAIT FOR RESPONSE LOW': - if sda != 0: - continue + self.wait({0: 'f'}) if self.is_valid('START HIGH'): self.putfs([0, ['Start', 'S']]) self.fall = self.samplenum self.state = 'WAIT FOR RESPONSE HIGH' else: - self.reset() + self.reset_variables() elif self.state == 'WAIT FOR RESPONSE HIGH': - if sda != 1: - continue + self.wait({0: 'r'}) if self.is_valid('RESPONSE LOW'): self.rise = self.samplenum self.state = 'WAIT FOR FIRST BIT' else: - self.reset() + self.reset_variables() elif self.state == 'WAIT FOR FIRST BIT': - if sda != 0: - continue + self.wait({0: 'f'}) if self.is_valid('RESPONSE HIGH'): self.putfs([1, ['Response', 'R']]) self.fall = self.samplenum self.bytepos.append(self.samplenum) self.state = 'WAIT FOR BIT HIGH' else: - self.reset() + self.reset_variables() elif self.state == 'WAIT FOR BIT HIGH': - if sda != 1: - continue + self.wait({0: 'r'}) if self.is_valid('BIT LOW'): self.rise = self.samplenum self.state = 'WAIT FOR BIT LOW' else: - self.reset() + self.reset_variables() elif self.state == 'WAIT FOR BIT LOW': - if sda != 0: - continue + self.wait({0: 'f'}) if self.is_valid('BIT 0 HIGH'): bit = 0 elif self.is_valid('BIT 1 HIGH'): bit = 1 else: - self.reset() + self.reset_variables() continue self.handle_byte(bit) elif self.state == 'WAIT FOR END': - if sda != 1: - continue + self.wait({0: 'r'}) self.putfs([3, ['End', 'E']]) - self.reset() + self.reset_variables()