X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fadf435x%2Fpd.py;fp=decoders%2Fadf435x%2Fpd.py;h=7810190d90f390bde596ae97c3a06fe172430290;hp=8c31648b873707d929a4fd01b26b078c364b2851;hb=912f4e8a245f014b312bfc90e4ec6dba256379d4;hpb=317eaa7fd83fb049db97e863a306992a34fcf490

diff --git a/decoders/adf435x/pd.py b/decoders/adf435x/pd.py
index 8c31648..7810190 100644
--- a/decoders/adf435x/pd.py
+++ b/decoders/adf435x/pd.py
@@ -135,6 +135,7 @@ class Decoder(srd.Decoder):
 
         if ptype == 'TRANSFER':
             if len(self.bits) == 32:
+                self.bits.reverse()
                 reg_value, reg_pos = self.decode_bits(0, 3)
                 self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
                     ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
@@ -146,8 +147,14 @@ class Decoder(srd.Decoder):
             else:
                 error = "Frame error: Wrong number of bits: got %d expected 32" % len(self.bits)
                 self.put(ss, es, self.out_ann, [ANN_WARN, [error, 'Frame error']])
-            self.bits = []
+            self.bits.clear()
 
         if ptype == 'BITS':
             _, mosi_bits, miso_bits = data
-            self.bits = mosi_bits + self.bits
+            # Cope with the lower layer SPI decoder's output convention:
+            # Regardless of wire transfer's frame format, .decode() input
+            # provides BITS in the LE order. Accumulate in MSB order here,
+            # and reverse before data processing when 'TRANSFER' is seen.
+            mosi_bits = mosi_bits.copy()
+            mosi_bits.reverse()
+            self.bits.extend(mosi_bits)