sr/srd: Add ChangeLog to ignore list, it's generated.

[libsigrokdecode.git] / type_logic.c

diff --git a/type_logic.c b/type_logic.c
index 5e499f4a8c9ee4cfa4feb1f4e6c4c6abd062c39c..bb4ef3d262b09b60bcca6617d86514b63ed20d5d 100644 (file)
--- a/type_logic.c
+++ b/type_logic.c
@@ -49,8 +49,7 @@ static PyObject *srd_logic_iternext(PyObject *self)
               logic->inbuf + logic->itercnt * logic->di->data_unitsize,
               logic->di->data_unitsize);
        for (i = 0; i < logic->di->dec_num_probes; i++)
-               probe_samples[i] =
-                   sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
+               probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
 
        /* Prepare the next samplenum/sample list in this iteration. */
        py_samplenum =