]> sigrok.org Git - libsigrokdecode.git/blobdiff - type_logic.c
rfm12: Avoid using the Python 'range' keyword as variable.
[libsigrokdecode.git] / type_logic.c
index 851a42ead51070334db360985b698962165df6be..a33d9976dc5d42ba7b216abab39d0581ab9ff91a 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * This file is part of the sigrok project.
+ * This file is part of the libsigrokdecode project.
  *
  * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
  *
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "sigrokdecode.h" /* First, so we avoid a _POSIX_C_SOURCE warning. */
+#include "libsigrokdecode-internal.h" /* First, so we avoid a _POSIX_C_SOURCE warning. */
+#include "libsigrokdecode.h"
 #include "config.h"
 #include <inttypes.h>
 #include <string.h>
 
-
-PyObject *srd_logic_iter(PyObject *self)
+static PyObject *srd_logic_iter(PyObject *self)
 {
-
        return self;
 }
 
-PyObject *srd_logic_iternext(PyObject *self)
+static PyObject *srd_logic_iternext(PyObject *self)
 {
-       PyObject *py_samplenum, *py_samples;
        srd_logic *logic;
-       uint64_t sample;
-       int i;
-       unsigned char probe_samples[SRD_MAX_NUM_PROBES];
+       PyObject *py_samplenum, *py_samples;
+       uint8_t *sample_pos, sample;
+       int byte_offset, bit_offset, i;
 
-       logic = (srd_logic *) self;
-       if (logic->itercnt >= logic->inbuflen / logic->di->unitsize) {
+       logic = (srd_logic *)self;
+       if (logic->itercnt >= logic->inbuflen / logic->di->data_unitsize) {
                /* End iteration loop. */
                return NULL;
        }
 
-       /* TODO: use number of probes defined in the PD, in the order the PD
-        * defined them -- not whatever came in from the driver.
-        */
-       /* Convert the bit-packed sample to an array of bytes, with only 0x01
+       /*
+        * Convert the bit-packed sample to an array of bytes, with only 0x01
         * and 0x00 values, so the PD doesn't need to do any bitshifting.
         */
-       memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->unitsize,
-                       logic->di->unitsize);
-       for (i = 0; i < logic->di->num_probes; i++) {
-               probe_samples[i] = sample & 0x01;
-               sample >>= 1;
+       sample_pos = logic->inbuf + logic->itercnt * logic->di->data_unitsize;
+       for (i = 0; i < logic->di->dec_num_channels; i++) {
+               /* A channelmap value of -1 means "unused optional channel". */
+               if (logic->di->dec_channelmap[i] == -1) {
+                       /* Value of unused channel is 0xff, instead of 0 or 1. */
+                       logic->di->channel_samples[i] = 0xff;
+               } else {
+                       byte_offset = logic->di->dec_channelmap[i] / 8;
+                       bit_offset = logic->di->dec_channelmap[i] % 8;
+                       sample = *(sample_pos + byte_offset) & (1 << bit_offset) ? 1 : 0;
+                       logic->di->channel_samples[i] = sample;
+               }
        }
 
        /* Prepare the next samplenum/sample list in this iteration. */
-       py_samplenum = PyLong_FromUnsignedLongLong(logic->start_samplenum + logic->itercnt);
+       py_samplenum =
+           PyLong_FromUnsignedLongLong(logic->start_samplenum +
+                                       logic->itercnt);
        PyList_SetItem(logic->sample, 0, py_samplenum);
-       py_samples = PyBytes_FromStringAndSize((const char *)probe_samples,
-                       logic->di->num_probes);
+       py_samples = PyBytes_FromStringAndSize((const char *)logic->di->channel_samples,
+                                              logic->di->dec_num_channels);
        PyList_SetItem(logic->sample, 1, py_samples);
        Py_INCREF(logic->sample);
        logic->itercnt++;
@@ -68,7 +73,8 @@ PyObject *srd_logic_iternext(PyObject *self)
        return logic->sample;
 }
 
-PyTypeObject srd_logic_type = {
+/** @cond PRIVATE */
+SRD_PRIV PyTypeObject srd_logic_type = {
        PyVarObject_HEAD_INIT(NULL, 0)
        .tp_name = "srd_logic",
        .tp_basicsize = sizeof(srd_logic),
@@ -77,4 +83,4 @@ PyTypeObject srd_logic_type = {
        .tp_iter = srd_logic_iter,
        .tp_iternext = srd_logic_iternext,
 };
-
+/** @endcond */